[SI-LIST] AW: Re: REG AC Capacitive Loading
- From: "Havermann, Gert" <Gert.Havermann@xxxxxxxxxxx>
- To: "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
- Date: Tue, 5 Jun 2012 14:05:15 +0000
Ken,
Wirewrap is not history yet.
Can you imagine that wire wrap is still used for low volume Backplanes
(especially in Power Systems)? We still sell quite a lot of wire wrap DIN Type
Backplane connectors into that area.
We also did some simulations on how to run 1.5GBps over wire wrap (that's been
a tough job).
BR
Gert
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-----Ursprüngliche Nachricht-----
Von: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] Im
Auftrag von Ken Wyatt
Gesendet: Dienstag, 5. Juni 2012 15:56
An: weirsi@xxxxxxxxxx
Cc: si-list@xxxxxxxxxxxxx
Betreff: [SI-LIST] Re: REG AC Capacitive Loading
Oh Steve, you're too much! As one of the knights from that period, I still own
a wire-wrap weapon from master Radio Shack, which I intend to display among my
treasured historical artifacts. Your reminisces from that epoch brought back
painful memories of troubleshooting mis-wires in a tangle of (transmission
line) spaghetti.
Cheers, Ken
_______________________
Kenneth Wyatt
Wyatt Technical Services LLC
Woodland Park, CO
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On Jun 5, 2012, at 1:16 AM, steve weir wrote:
> Most MSI is from the Age of Augat, when armies of gnomes fought using
> ancient weapons they called wire-wrap guns. During that epoch,
> digital engineers heard rumors and stories of mythical beasts called
> transmission lines that only the few such as Seymour of Chippewa dared tame.
>
>
> Steve
>
> On 6/4/2012 11:01 PM, Tesla wrote:
>> Hi, Steve
>>
>> What is "MSI from 1975"?
>> Does it have some stories?
>>
>> Thanks.
>>
>> Tesla.
>>
>>
>>
>>
>> At 2012-06-02 21:42:46,"steve weir"<weirsi@xxxxxxxxxx> wrote:
>>> 50pF for a single input sounds like someone cut and pasted a spec
>>> from inside some prehistoric cave painting. Is the buffer made with
>>> MSI from 1975? You should seriously question any values above about 8pF.
>>>
>>> Steve.
>>> On 5/31/2012 8:59 PM, Vinothkumar D wrote:
>>>> Hello Everyone,
>>>>
>>>> I have a problem in AC loading in which the Cout of FPGA<< Cin of a Bus
>>>> controller. I have used a buffer between FPGA and Bus controller still I
>>>> could not meet ac loading requirements.
>>>> Eg:
>>>> FPGA Cout = 5pF
>>>> Buffer Cin = 5pF and Cout = 50pf
>>>> Each Bus controller Cin = 50pF
>>>> Total Bus controllers Cin = 150pf
>>>>
>>>> Now I have connected the ADD/DATA and control pins through Buffer which is
>>>> driving three bus controllers, I am meeting the ac loading requirements.
>>>>
>>>> Will it create any timing issue . Please help me on this.
>>>>
>>>> Regards
>>>> Vinothkumar.D
>>>> E-mail ID : Vinothkumar.D@xxxxxxxxxx
>>>>
>>>> Larsen& Toubro Limited
>>>>
>>>> www.larsentoubro.com
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>>>
>>> --
>>> Steve Weir
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>>
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>
>
> --
> Steve Weir
> IPBLOX, LLC
> 150 N. Center St. #211
> Reno, NV 89501
> www.ipblox.com
>
> (775) 299-4236 Business
> (866) 675-4630 Toll-free
> (707) 780-1951 Fax
>
> All contents Copyright (c)2012 IPBLOX, LLC. All Rights Reserved.
> This e-mail may contain confidential material.
> If you are not the intended recipient, please destroy all records and
> notify the sender.
>
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- » [SI-LIST] AW: Re: REG AC Capacitive Loading - Havermann, Gert
