[SI-LIST] Re: AW: Re: Impact on Copper Thieving on 10G Routing
- From: "Lee " <leeritchey@xxxxxxxxxxxxx>
- To: <Gert.Havermann@xxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Mon, 10 Mar 2014 10:00:37 -0700
I have built similar size backplanes with no problems like you cite. I
have a few in my lab right now. They are not built with low flow resins.
Haven't seen he problem you describe so far.
-----Original Message-----
From: Havermann, Gert
Sent: Monday, March 10, 2014 1:45 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] AW: Re: Impact on Copper Thieving on 10G Routing
Lee,
I agree that complex Electronic boards don't need fill on inner Layer, but
for Backplanes inner layer fill does make sense as the Layer count is high,
and the routing channels lie on top of each other. Since Resin flow is very
low for high layer count Prepregs (usually now flow PP are used), thickness
variations can happen easily. This is nicely avoided by adding copper
fragments (rather than solid plane pour).
I've had Backplanes where even the 2nd inner Layer somewhat "watermarked" on
the Top surface due to thin PP and not using fill.
BR
Gert
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-----Ursprüngliche Nachricht-----
Von: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] Im
Auftrag von Lee
Gesendet: Freitag, 7. März 2014 18:22
An: sij99@xxxxxxxxx; si-list@xxxxxxxxxxxxx
Betreff: [SI-LIST] Re: Impact on Copper Thieving on 10G Routing
Seems like there is a lot of confusion as to what thieving is. So, here is
what it is.
Thieving is copper added to outer layers of a PCB to create a uniform
distribution of copper across the surface. The reason this is done is to
make sure the copper plating in the holes is uniform. If the copper
distribution in the artwork is not uniform, areas with little exposed copper
will plate very heavy while areas with large amounts of copper, such as BGAs
or connector pin fields will not plate properly. So, "thieving" steals some
of the plating current that would otherwise concentrate on features that are
sparse and be spread thin in areas with areas that are dense with features.
Again, thieving is an outer layer only process. All of the discussions that
mention doing things to inner layers are not thieving. They are signal
layer fills to even out the resin flow from the prepreg. I have designed
thousands of complex PCBs with many signal layers in each one and have never
encountered a stackup that required inner layer signal layer fill to achieve
a usable, flat PCB.
Long ago, before call plates were inserted between PCBs in a laminator
opening, it was possible to have PCBs with low spots where there was little
copper on inner signal layers. That problem has pretty much gone away, so
it is not necessary to do inner layer fills.
When a fabricator is allowed to add thieving to outer layers, one only need
to keep it away from other features on that layer to comply with typical
spacing standards and away from traces enough that it does not adversely
affect impedance. If the next layer down is a plane layer, that is all that
is needed. If the next layer down is a signal layer (buried microstrip)
thieving should not be placed over traces in the buried layer.
I hope this helps clear up this issue.
Lee Ritchey
-----Original Message-----
From: Jack Si
Sent: Thursday, March 06, 2014 11:53 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Impact on Copper Thieving on 10G Routing
Hi Experts,
What are the major impact created by Copper Thieving in the 10G signals and
the precautions to avoid it.
Thanks and Regards,
Jack
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