[SI-LIST] AW: Re: DDR termination
- From: <hermann.ruckerbauer@xxxxxxxxxxxx>
- To: <fred@xxxxxxxxxxxxx>, <electronbob2@xxxxxxxxxxxxx>
- Date: Fri, 14 May 2004 10:33:31 +0200
Hello,
here my cent ...=20
The end termination of the DDR1 DQ bus (might be the same or different =
value for CA) is varing quite a bit for different mobos. I have seen in =
the beginning of DDR1 very low resistances (27 Ohm), while the value =
increased over time up to 50 and 60 Ohm.
The multi drop memory bus is not very clean, and therefore the =
termination value is just a trade off between timing and voltage margin.
In the beginning mobo manufacteres tried to implement many slots (up to =
4), what is resulting in a lot of disturbance on the bus. To reduce this =
effect a stronger termination value was usefull.=20
Now when going to higher speeds the number of slots is reduced. And here =
it seems to be heplfull to have a higher termination resistance to =
increase voltage margin. But even if a higher value would result in =
better margins, as long a system is working it will stay with any value =
which was working so far.
So I think the values used for termination are a mix between optimizing =
a multi drop topology (timing vs. voltage margin) vs. and some =
historicly (2 years ;-) ) used termination values.
Regarding the serial termination (R before the fist slot on the mobo) I =
would expect this is included in most DDR1 Mobo, but it should be =
removed in DDR2 Motherbards with ODT.
For DDR2 there should be only a parallel termination on the CA bus at =
the end of the bus. DQ lines should have no end termination of the bus =
(parallel termination), as they should use the OnDieTermination!
Hermann
-----Urspr=FCngliche Nachricht-----
Von: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] =
Im Auftrag von Fred Townsend
Gesendet: Donnerstag, 13. Mai 2004 22:18
An: Bob McNamara
Cc: 'si-list@xxxxxxxxxxxxx'
Betreff: [SI-LIST] Re: DDR termination
OK this sounds like split terminations on balanced (differential)=20
lines. In that case the circuit would see twice the "R" value. Twice=20
27 would be a 54 ohm surge impedance which is reasonable. 27 ohm traces =
are difficult if not impossible to make. My answer as to why the=20
variation in values still applies, i.e. match to the driver, trace, and=20
rise time requirements.
Fred Townsend
Bob McNamara wrote:
>No, I didn't confuse the series and parallel
>terms. The series R's have visible surface etch
>leading off to the chipset. The parallel R's have
>a visible connection to a Vtt island. They look
>distinctly different.
>
>All MB's have parallel termination for their DDR
>memory channel(s). Most (but not all) also have
>series termination. Some use a small cap on the address/command=20
>signals and no series R, while others just have artwork for the cap.
>
>The parallel R's vary from 27 Ohm to 68 Ohm. The
>series R's were 10 Ohm, 22 Ohm, or not present (or
>0 Ohms in at least one case).
>
>Bob
>
>--- Fred Townsend <fred@xxxxxxxxxxxxx> wrote:
> =20
>
>>Good question, Bob, but you made an incorrect
>>assumption. The terminations are series, not
>>parallel. Since series terminations increase
>>rise time and reduce signal levels, they are
>>usually less than an optimum match. The
>>impedance of the source is also a factor since
>>its impedance is added to the series terminator.
>>So the answer to your question is the terminator
>>value varies under the influence of clock speed,
>>source impedance, trace width (impedance) and
>>load (fanout).
>>
>>Fred Townsend
>>
>>Bob McNamara wrote:
>> =20
>>
>>>I was looking over motherboards at Fry's
>>>yesterday and noticed quite a wide variation
>>>in the resistor values used for parallel
>>>termination: 27, 33, and 56.
>>>
>>>Can anybody tell me why there is such a wide
>>>variation?
>>>
>>>Thanks,
>>>
>>>Bob
>>>
>>> =20
>>>
>
>
> =20
>
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to: =
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List FAQ wiki page is located at:
http://si-list.org/wiki/wiki.pl?Si-List_FAQ
List technical documents are available at:
http://www.si-list.org
List archives are viewable at: =20
//www.freelists.org/archives/si-list
or at our remote archives:
http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
=20
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List FAQ wiki page is located at:
http://si-list.org/wiki/wiki.pl?Si-List_FAQ
List technical documents are available at:
http://www.si-list.org
List archives are viewable at:
//www.freelists.org/archives/si-list
or at our remote archives:
http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
Other related posts:
- » [SI-LIST] AW: Re: DDR termination
