[SI-LIST] AW: Re: AW: AW: PCB issue

  • From: "Havermann, Gert" <Gert.Havermann@xxxxxxxxxxx>
  • To: "steve weir" <weirsi@xxxxxxxxxx>, si-list@xxxxxxxxxxxxx
  • Date: Fri, 8 Jul 2011 13:45:32 +0200

Steve,

thats tru. I was just illustrating my "8GB/several mm" statement from the mail 
before as requested by Nirmesh.

BR
Gert


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-----Ursprüngliche Nachricht-----

Von: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] Im 
Auftrag von steve weir
Gesendet: Freitag, 8. Juli 2011 13:37
An: si-list@xxxxxxxxxxxxx
Betreff: [SI-LIST] Re: AW: AW: PCB issue

Gert, even if the via lengths were short, any significant distance between 
either the transmitter and the near via, or from the far via to the receiver, 
and substantial signal energy will bounce around each of 
the four segments.   In the damned if you do, damned if you don't 
department, if the vias are short and the path looks like a contiguous
25 Ohm path, and both ends are terminated, then the voltage reflection 
coefficient is 33% at each end, and there is still 11% reflected after a 
full round trip.   Moving the vias away from either the transmitter 
and/or the receiver only makes the problems worse unless the vias plus side 
track path become so short as to be negligible to the signal energy content.

Steve

On 7/8/2011 4:18 AM, Havermann, Gert wrote:
> Hi Nirmesh,
>
> Look at this sketch of a cross section of Pugals setup with long via distance 
> between layers:
> ---|-------------------------------|-------
>      |                                      |
>      |                                      |
>      |-------------------------------|
>
> You see that the effective tracelength on the lower trace is much longer than 
> on the upper trace. In the extreme case where the electrical length 
> difference is in the range of half a Biltength, then most of the signal will 
> cancel itself out. For 8Gbps the length difference per via would have to be 
> apprx. 18mm (for a complete cancellation). But even half a bitlength will 
> mean many lost bits, as the eye width is cut in half, and thinking about some 
> 10mm thick backplanes, this is in a realistic region already. Things are 
> already getting bad when 1/4 bitlength is exceeded, and that’s 4.5mm length 
> difference per via. For Backplanes very reasonable PCB thickness.
>
> Another effect is that both paths resonate at different frequencies (and they 
> will resonate strongly due to the strong impedance mismatch caused by 
> splitting and combining the traces).
>
> BR
> Gert
>
>
> --------------------------------------------------------------------------
> Absender ist HARTING Electronics GmbH&  Co. KG; Sitz der Gesellschaft: 
> Espelkamp; Registergericht: Bad Oeynhausen; Register-Nr.: HRA 5596; 
> persönlich haftende Gesellschafterin: HARTING Electronics Management GmbH; 
> Sitz der Komplementär-GmbH: Espelkamp; Registergericht der Komplementär-GmbH: 
> Bad Oeynhausen; Register-Nr. der Komplementär-GmbH: HRB 8808; 
> Geschäftsführer: Edgar-Peter Duening, Torsten Ratzmann, Dr. Alexander Rost
> -----Ursprüngliche Nachricht-----
>
> Von: Nirmesh Kumar AWASTHI [mailto:nirmesh.awasthi@xxxxxx]
> Gesendet: Freitag, 8. Juli 2011 12:20
> An: Havermann, Gert; Newbie Pugal; si-list@xxxxxxxxxxxxx
> Betreff: RE: [SI-LIST] AW: PCB issue
>
> Hello Gert,
>
> Please illustrate more on, why you emphasized on " If the layers aren't too 
> far apart (I'm talking about several mm) and the speed is below 8Gbps".
>
> Thanks in advance.
> Nirmesh.
>
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On 
> Behalf Of Havermann, Gert
> Sent: Friday, July 08, 2011 3:04 PM
> To: Newbie Pugal; si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] AW: PCB issue
>
> Hi Pugal,
>
> you are right, the resulting impedance of two parallel 50Ohm lines is 25 Ohm. 
> If the layers aren't too far apart (I'm talking about several mm) and the 
> speed is below 8Gbps, your setup will react exactly like a single 25 Ohm line 
> (increased losses and reflections).
>
> You can fix this problem on the manufactured boards with backdrilling to vias 
> to the closest signal layer. By this you disconnect one signal trace from the 
> via. This backdrilling can be done by hand if you have good drillbits and a 
> robust stand-drill (I wouldn't do it with hand drill or cheap hand drill 
> stand). The drilldepth has to be taken from the stackup. Drill in several 
> small steps and check the line impedance to verify that you only hit one 
> trace instead of disconnecting both.
> If you don't have the right equipment, ask you PCB maker if they would be 
> willing to backdrill with their depth controlled drilling machines.
>
> Good luck.
> Gert
>
>
> --------------------------------------------------------------------------
> Absender ist HARTING Electronics GmbH&  Co. KG; Sitz der Gesellschaft: 
> Espelkamp; Registergericht: Bad Oeynhausen; Register-Nr.: HRA 5596; 
> persönlich haftende Gesellschafterin: HARTING Electronics Management GmbH; 
> Sitz der Komplementär-GmbH: Espelkamp; Registergericht der Komplementär-GmbH: 
> Bad Oeynhausen; Register-Nr. der Komplementär-GmbH: HRB 8808; 
> Geschäftsführer: Edgar-Peter Duening, Torsten Ratzmann, Dr. Alexander Rost 
> -----Ursprüngliche Nachricht-----
>
> Von: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] Im 
> Auftrag von Newbie Pugal
> Gesendet: Freitag, 8. Juli 2011 08:13
> An: si-list@xxxxxxxxxxxxx
> Betreff: [SI-LIST] PCB issue
>
> Hi All,
> I'm facing some issues in the manufactured PCB due to the error in the 
> routing stage.
>
> The
>   error is a single net is routed in two different layers. The signal is 
> running from a source pin to the receiver pin in two different layers and 
> each is 50-ohms impedance designed individually.
>
>
> Here my
>   question since the two traces are shorted at receiver and driver pins the 
> effective impedance will come down to zo/2 corrcet me if i'm wrong.
> Is it possible to achieve 50-ohms in some way in the actual manufactured  
> board?
>
> What could be the other problems we can expect for the above scenario for the 
> failing of signals?
>
>
> Thanks
> Pugal
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  • » [SI-LIST] AW: Re: AW: AW: PCB issue - Havermann, Gert