[SI-LIST] AW: Maximum trace length of 6.25Gbps SerDes
- From: "Havermann, Gert" <Gert.Havermann@xxxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Wed, 12 May 2010 08:48:13 +0200
assuming 5-6-5 routing and good connectors with decent footprint Design, 20"
maximum trace length (chip-to-chip) would be a good starting point. If you need
more, do the simulations first.
BR
Gert
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Von: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] Im
Auftrag von Mashook Ahamed Usman
Gesendet: Mittwoch, 12. Mai 2010 03:52
An: si-list@xxxxxxxxxxxxx
Betreff: [SI-LIST] Maximum trace length of 6.25Gbps SerDes
Dear Experts,
Good day!
Currently I am assigned to collect the routing tips for 6.25Gbps serdes
interface. Since we are not doing the simulation at the current draft we would
like to go with a rule of thumb if possible.
The trace has to start from the linecard, run through the backplane and
terminate in the switch card which is an usual scenario.
Considering a 100 ohm controlled impedance in FR4 material, what would be the
maximum length a 6.25Gbps serdes can travel from line card to the switch card.
The pre emphasis and equilalizer is in build in the chipset no need to put
outside.
Thank you very much for your time.
M Usman
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