Hi,
On boards that have multi layer staggered microvias, most inner copper
foil layers get additional plating. If only through vias are used in a
design (with backdrilling), then the inner copper layers will just be
copper foil that comes from the material supplier with no added
plating.
So, I suspect the insertion loss dB/inch@13GHz is affected by the
choice of doing staggered microvias versus only using through
mechanically drilled vias. Because insertion loss (fitted attenuation)
is probably affected by the conductivity of the plating too, not only
by roughness.
Do you have numbers of how much % the loss changes by this choice?
Regards,
Istvan Nagy
On 7/1/22, Scott McMorrow <scottmcmorrow@xxxxxxxxx> wrote:
Without an additional rolling and annealing process it's pretty much------------------------------------------------------------------
impossible for electroplated copper to be equivalent to IACS 100
conductivity copper. The electroplating process is necessarily grainy and
has inclusions that depend upon the current density used in plating and the
amount of annealing done the grains of copper never fully "smush" together.
Similar issues occur with sintered copper used in 3D printing.
We've measured room temperature conductivity as low as 4e7 S/m for
electroplated copper in packaging. But we've heard reports of even lower
values. I agree this is hard to measure, but it's possible.
We've also seen boards fabricated with low purity copper from off-shore
foil suppliers. Fortunately, simple deembedded stripline trace loss
measurement will expose copper problems.
Gert is correct.
Have a happy and safe fourth of July weekend and don't poke your eye out.
Scott
On Fri, Jul 1, 2022, 1:55 PM Doug Brooks <dbrooks9@xxxxxxxxxxxxxxx> wrote:
In our book, PCB Design Guide to Via and Trace Currents and Temperatures
(Amazon) we devote an ENTIRE appendix (B) to the problems of measuring
resistivity. We conclude it simply can't be measured accurately outside
a very well equipped laboratory, and explain in detail why (along with
experimental results.) The problems are (1) actual resistance, to the
precision required, is very difficult to measure, and (2)
cross-sectional area is even harder to determine accurately. You
absolutely cannot take the nominal trace dimensions as the appropriate
measure.
The 0.0172 value is typically given for electrodeposited (plated) copper
(at 20 degrees C). It is nearly pure copper. Rolled copper is derived
from a copper ingot which will have some impurities. Rolled copper
resistivity will be higher than electrodeposited copper. The 0.0185
value is an estimate of what rolled copper will probably be. It should
be pretty close.
I expect your "measured" value is way too high unless you are at a
highly elevated temperature.
Doug Brooks
Havermann Gert (Gert.Havermann) wrote:
Hi,uses textbook values by default, or measured copper foil. The PCB copper
the textbook values are for pure copper, and most simulation software
isn't pure, especially the electroplated outer layers, so it has higher
resistance than pure copper. Best practice is to measure the resistance
(can vary between laminate and PCB manufacturers) and use this value for
future simulations.
www.HARTING.com
BR
Gert
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Auftrag von ??
-----Ursprüngliche Nachricht-----
Von: si-list-bounce@xxxxxxxxxxxxx <si-list-bounce@xxxxxxxxxxxxx> Im
Gesendet: Donnerstag, 30. Juni 2022 10:30from 0.0172 to 0.0185. We measured resistivity of PCB trace is about
An: si-list@xxxxxxxxxxxxx
Cc: tommy.huang@xxxxxxxxxx
Betreff: [EXTERNAL] [SI-LIST] conductor resistivity for SI simulation
Hi Expert,
We saw default resistivity value of copper in different simulation tool
0.021
by resistance and cross-section. This 20% difference resistivity
introduce
about 8% loss difference below 10GHz, about 5% difference higher than
10GHz
from my simulation tool.
Is there any recognized value for insertion loss simulation orrecommendation method to characterize correct resistivity of PCB trace?
Any advise is appreciated
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