Hi Istvan,
Without knowing more about the particular process that European PCB shop was
using, it is very hard to tell, what exactly they did. They may have used a
double pass plating process, where the small vias got plated twice and the
larger vias plated only once (by drilling them between the 1st and 2nd
plating step). But I would not understand why anyone would do this.
All PCB shops are driven by cost, cost, cost. So they try to use the most
cost effective process. Any additional process steps, longer plating
exposure times,... cost more money, so everybody tries to avoid them.
As explained in my original statement, it is most difficult to get the
copper in the small vias. The larger vias are easier (unless we talk about a
single, isolated small hole compared to a large number of bigger holes that
are very close together). So PCB shops will try to get enough copper in the
small holes (to satisfy OEM specs regarding Cu plating). This typically
automatically guarantees that enough copper is in the larger holes.
One limitation are larger press fit holes with very tight tolerances. With
this approach, the plating in the larger holes may already exceed what is
acceptable for FHS minimum sizes. Because of this, it may be necessary to
use a special plating process that limits the plating into the larger
pressfit holes but still get enough copper in the small via holes.
But then again, after 20 years on the PCB manufacturing side, I can
definitively say, we always had less copper in small vias compared to large
PTHs.
Best regards,
alex
----------------------------------------------------------------------------------------------------------------------------------------
Alexander Ippich
Senior Signal Integrity Engineer
OEM Marketing Europe
Tel.: +49 170 / 63 68 571
e-mail: alexander.ippich@xxxxxxxxxxxxxxx
web: www.isola-group.com
-----Ursprüngliche Nachricht-----
Von: Istvan Nagy [mailto:buenoshun@xxxxxxxxx]
Gesendet: January 05, 2016 04:58 AM
An: Lee Ritchey; alexander.ippich@xxxxxxxxxxxxxxx; saardrimer@xxxxxxxxx
Cc: 'SI'; 'Jeff Loyer'
Betreff: Re: [SI-LIST] AW: Re: How to specify via hole sizes
Hi,
Several years ago I was working in Europe and with local PCB fabs. One of
them told me that data with the thinner hole more copper. I didn't
misunderstand it.
Today I asked my current Taiwanese fab and they said:
10mil-drill vias: copper thickness is 1.0mil, larger PTH holes: copper
thickness is 1.1mil.
Either the data was inaccurate (I doubt it) or their process is different.
Regards,
Istvan Nagy
-----Original Message-----
From: Lee Ritchey
Sent: Monday, January 04, 2016 9:00 AM
To: alexander.ippich@xxxxxxxxxxxxxxx ; buenoshun@xxxxxxxxx ;
saardrimer@xxxxxxxxx
Cc: 'SI' ; 'Jeff Loyer'
Subject: RE: [SI-LIST] AW: Re: How to specify via hole sizes
Well said!
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Alexander Ippich
Sent: Sunday, January 3, 2016 11:47 PM
To: buenoshun@xxxxxxxxx; saardrimer@xxxxxxxxx; Lee Ritchey
<leeritchey@xxxxxxxxxxxxx>
Cc: SI <si-list@xxxxxxxxxxxxx>; Jeff Loyer <jeff.loyer@xxxxxxxxxx>;
Alexander Ippich <alexander.ippich@xxxxxxxxxxxxxxx>
Subject: [SI-LIST] AW: Re: How to specify via hole sizes
Istvan,
This looks like some wrong information. Smaller vias are always getting less
copper plating than larger vias (in the same plating step). Think about the
electrical fields in a narrow tunnel that has metalized side walls. You will
get a much lower current density in the small vias, and as a result less
plating deposition. In addition, the exchange of the plating fluid is worse
in small vias.
Bottom line, if small and large vias are plated in the same step, PCB
manufacturers will adapt their plating process to get the minimum copper
requirement fulfilled for the small vias and you will see thicker copper in
the larger vias.
And as Lee already pointed out, there are some fabricators that have better
uniformity and some with worse uniformity. Design is already playing a role
(dense areas get less copper than isolated features) and there are ways to
optimize like thieving patterns.
But in general, if somebody is claiming more copper in small vias and less
copper in large vias, something is very very strange (unless you talk about
copper filling of vias).
Best regards,
alex
----------------------------------------------------------------------------------------------------------------------------------------
Alexander Ippich
Senior Signal Integrity Engineer
OEM Marketing Europe
Tel.: +49 170 / 63 68 571
e-mail: alexander.ippich@xxxxxxxxxxxxxxx
web: www.isola-group.com
-----Ursprüngliche Nachricht-----
Von: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] Im
Auftrag von Istvan Nagy
Gesendet: December 30, 2015 10:46 PM
An: saardrimer@xxxxxxxxx; Lee Ritchey
Cc: SI; Jeff Loyer
Betreff: [SI-LIST] Re: How to specify via hole sizes
Different hole sizes get different amount of copper. One fab told me that
with their process the smallest via holes get 2mils on the walls, while the
larger holes get only 1mil.
Regards, Istvan Nagy, mobile
*** Sent from my BLU smartphone device *** On Dec 30, 2015 9:04 AM, Lee
Ritchey <leeritchey@xxxxxxxxxxxxx> wrote:
To unsubscribe from si-list:
I always specify drill size. If there is a hole that requires a
finished hole size, I add 4 mils to get the drill size. This allows a
minimum of 1 mil copper in the hole wall which is what most of require.
Works great!
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of saar drimer
Sent: Tuesday, December 29, 2015 12:55 PM
To: buenoshun@xxxxxxxxx
Cc: SI <si-list@xxxxxxxxxxxxx>; Jeff Loyer <jeff.loyer@xxxxxxxxxx>
Subject: [SI-LIST] Re: How to specify via hole sizes
This is a great example where tools actively limit design creativity.
What possibly led to a situation where only specifying one dimension
is satisfactory? This isn't a manufacturing limitation.
It's worse when you want to do something more creative, like having
vias that have different ODs for each layer. I've done this for visual
reasons (using PCBmodE where vias are components), and I'm not sure
there's a legitimate functional reason to do that (is there?)
Cheers,
Saar.
On Tuesday, December 29, 2015, Istvan Nagy <buenoshun@xxxxxxxxx> wrote:
Jeff,
most fabs will manufacture to your ID or OD if you tell them which
one you want. The design tools like allegro and altium works best
wit OD, and you can only specify one or the other. Tools drill file
formats and drill tables only support one diameter per hole. For
designing better use OD as it helps the drc to make sure no pads
drilled away and no drill to xx clearances were violated. The wall
thickness depends on the fab and the hole size, an even the same fab
will give you different numbers each time.
i think the safest is to specify OD and use worst case thin for PI
while worst case thick wall for PTH component pins.
Regards, Istvan, mobile
*** Sent from my BLU smartphone device *** On Dec 29, 2015 11:15 AM,
Jeff Loyer <jeff.loyer@xxxxxxxxxx <javascript:;>>
wrote:
(O.D.,
One thing that has bothered me forever is the ambiguity in
specifying via hole sizes. To my mind, there are instances where
I might want to carefully specify either, or both of, the outer
and inner diameters
I.D., respectively) of the via “columnâ€. But, that seemsnot
difficult (if
impossible) to do with current common drill specifications (what acopper
“finished hole size†is seems to depend on context, some folks
enter the approximate drill size here). Can folks tell me how
they ensure they get the correct diameters for the following cases:
1) Signal integrity: I care about the O.D. This is going to
be
(approximately) the size of actual drill used.
2) Mounting holes: I care about the O.D. This is going to be
(approximately) the size of actual drill used.
3) Press Fit connectors: I care about the I.D. This is the
actual drill size minus plating thickness.
4) Power Integrity: I care about both, I want to know the
total
connecting my layers.with
What does your drill chart look like that ensures you get what you
need?
I’ve used “drill size†with some tolerance plus a
“finished hole sizeâ€
its tolerance, but that seems ambiguous. At this point, I thinkto
we need
specify a “hole diameter†with a corresponding tolerance, andeach
a plating thickness range. While I would prefer to specify both O.D.
and I.D.,
with its corresponding tolerance, I’m told that folks in thewon’t
industry
know what I’m talking about if we do it that way. What hasfor
worked best
folks?to,
Also, if someone has a key contact within IPC that I should be
talking
I welcome that information too (please send it to me only to limitunwanted
distribution of anyone’s e-mail).Subject field
Thanks,
*Jeff Loyer*
Signal and Power Integrity Product Manager, Altium
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