[SI-LIST] AW: AW: Re: Flooded Vias vs Thermal Relief

  • From: "Havermann, Gert" <Gert.Havermann@xxxxxxxxxxx>
  • To: si-list@xxxxxxxxxxxxx
  • Date: Tue, 23 Mar 2010 16:27:12 +0100

Hi Jim,

thank you for sharing you experience. I should be more detailed on SI-list, but 
time is precious, and the field is huge and complex (and it depends...).

I can see why you haven't seen issues yet (and might never run into them). 
Flooding a BGA footprint often isn't that much of an issue. Due to the high via 
count, the GND planes are perforated, and whats left looks very similar to a 
thermal relief, doesn't it? The more perforations you have in the GND planes, 
and the less GND planes you have, minimizes the chance of errors. Densily 
packed Electronic cards might very often be okay even with high layer count, 
while Backplanes are very critical in this regard, because there the GND planes 
are massive. 
I should have stated this.

BR
Gert


  
 

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Von: James F. Herrmann [mailto:jherrmann@xxxxxxxxxxxxxxxx] 
Gesendet: Dienstag, 23. März 2010 15:39
An: Havermann, Gert
Betreff: RE: [SI-LIST] AW: Re: Flooded Vias vs Thermal Relief

Hello Gert - Thank you for sharing your insight and experiences. Many of my 
designs have been in the 12-layer to 16-layer range, typically with 1 mm and/or 
0.8 mm BGA (and no thermal relief). I have not received any DFM feedback from 
the Contract Manufacturers that there are reflow process issues with these 
assemblies. I agree that it is very likely that they are processed with a 
longer total dwell time within the IR reflow oven (the CMs involved do not have 
vapor phase equip). There have been no long term reliability issues with these 
assemblies with likely upwards of 100K total assemblies in the field for more 
than 5 years now. I have requested a more detailed assessment of the reflow 
profile of a recent 16-layer design and will plan to share anything of 
significance with the list.

Regards,

Jim Herrmann


-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On 
Behalf Of Havermann, Gert
Sent: Monday, March 22, 2010 4:40 AM
To: SI-LIST
Subject: [SI-LIST] AW: Re: Flooded Vias vs Thermal Relief

Jim, Michael,

Reflow also needs thermal spokes for good solderability. Especially thick, high 
layer count PCBs suck the heat into the center, cooling the solder joint. This 
means that you need a longer oven time, or more heat. Both means more stress 
for the components, and potentially more cost. With thermanls you avoid costly 
process changes while maintaining high yield. These "problem boards" can most 
often just be reliably soldered in vapor phase, where the solder process stops 
automatically when all parts have the same temperature. Still you potentially 
need a longer process time to maintain high yield, but the thermal stress is 
much lower than in a Reflow process.
As I said, this is a problem for High layer count and especially many GND 
planes. For small boards (up to 6 or maybe 8 Layers), you may not run into 
issues deleting the thermals. I use thermals even on those PCBs, because I like 
to be able to Hand solder or rework my circuits.

BR
Gert


  
 

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Absender ist HARTING Electronics GmbH & Co. KG; Sitz der Gesellschaft:
Espelkamp; Registergericht: Bad Oeynhausen; Register-Nr.: HRA 5596; persönlich 
haftende Gesellschafterin: HARTING Electronics Management GmbH; Sitz der 
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8808; Geschäftsführer: Torsten Ratzmann -----Ursprüngliche Nachricht-----


Von: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] Im 
Auftrag von James F. Herrmann
Gesendet: Freitag, 19. März 2010 16:08
An: 'Michael Greim'
Cc: 'SI-LIST'
Betreff: [SI-LIST] Re: Flooded Vias vs Thermal Relief

Michael,

Were on the same page - one follow-up question on your "hint 2":
If we assume an oven reflow solder process (and not wave solder) then is there 
really a concern with vias attached to SMT land pads acting as a detrimental 
thermal sink? My intuition is that with an oven reflow process the entire board 
structure is brought up to the reflow temperature, thereby eliminating the 
internal plane thermal sink concern (which was an obvious and real issue with 
wave solder process). Hopefully, a solder process expert can weigh in...
Thanks,

Jim Herrmann






-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On 
Behalf Of Michael Greim
Sent: Friday, March 19, 2010 10:31 AM
To: wjcsongr@xxxxxxxxxxxxxxxxxxx
Cc: Jack Olson; SI-LIST; si-list-bounce@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Flooded Vias vs Thermal Relief

Hmmmmm,
How to address this one while being cordial. Ok, for starters, sarcasm cannon 
set on stun........

OK, let's start with the low hanging fruit and move up.
We certainly don't want things to be difficult for you while checking, so leave 
the thermals on for your check and then change them when you are done.
The best of both worlds right?  As you said, it's only a mouse click.

I humbly suggest that you track down the origin of thermal attach vias and why 
they exist. I will give ya a hint.  Through hole components.  Hint two, a smt 
lead and fanout to via is also like a thermal attach.

Have slicing and dicing simulation or tests been performed that show the impact 
of thermals on power distribution?  Yes.
If packed tightly and deeply enough you have a fraction of the conductor
cross section that you thought you had.   With high enough
current, bad things can and will happen regarding conductor temp rise.

Never back a methodology with the argument, "Well that's the way that I've 
always done it and its easier."


Best Regards,

Michael C. Greim

And all this science they don't understand Is just my job six days a week.....

We will either find a way or make one   -Hannibal

In the middle of every difficulty lies opportunity   -Al Einstein


 Jack Olson <pcbjack@xxxxxxxxx>
> Sent by: si-list-bounce@xxxxxxxxxxxxx
> 03/19/2010 08:43 AM
>
> To
> SI-LIST <si-list@xxxxxxxxxxxxx>
> cc
>
> Subject
> [SI-LIST] Flooded Vias vs Thermal Relief
>
>
>
>
>
>
> Greetings,
> I am being instructed to flood all vias instead of using thermal 
> relief, to get a "better" connection to planes. I've typically used 
> thermal reliefs simply because they are easier to see in checking or 
> design reviews (but its only one mouse click for me to change them so 
> I'm not really complaining).
>
> but it got me thinking.....
>
> Have any test results ever showed that spokes have a significant 
> impedance or anything that can change circuit performance?
> (and I'm referring to 12mil plated through-hole vias on boards 100MHz
> max)
>
> I don't remember anyone ever talking about that.
>
> surfin' the learnin' curve,
> Jack
>
>
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  • » [SI-LIST] AW: AW: Re: Flooded Vias vs Thermal Relief - Havermann, Gert