[SI-LIST] 答复: AW: AW: Re: AW: Shielding vias around microstrip
- From: "Longjun Zhou(LUXSHARE-ICT)" <Longjun.Zhou@xxxxxxxxxxxxxxxx>
- To: "Havermann, Gert" <Gert.Havermann@xxxxxxxxxxx>, "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
- Date: Thu, 27 Nov 2014 08:36:04 +0000
Thank you very much, Gert. I got it . I think the vias used in most the PCBs I
saw are mainly used to control impedance because there are arranged in very
short distance, not for shielding purpose.
Zhou Longjun 周龙军
EE Team / Enterprise Business Group
LUXSHARE-ICT Precision Industry Co., Ltd.
T：+86 769 89089000 Ext 86024 M：+86 13620065253
E：Longjun.zhou@xxxxxxxxxxxxxxxx
A：No. 17 KuiQing Road, QingHuang Industrial Zone, QingXi Town, DongGuan City,
GuangDong, China
-----邮件原件-----
发件人: Havermann, Gert [mailto:Gert.Havermann@xxxxxxxxxxx]
发送时间: 2014年11月27日 15:56
收件人: Longjun Zhou(LUXSHARE-ICT); si-list@xxxxxxxxxxxxx
主题: AW: [SI-LIST] AW: AW: Re: AW: Shielding vias around microstrip
If you, for whatever reason, need stitching vias next to the Microstrip line,
then you need to follow the rules dictated by the reason to use Stitching vias.
It all depends on why you are using them. If you need them for Schielding, then
they should be placed as far away from the trace as possible, because it is
distance that makes the shielding and not the vias. If you do it to try to
control the impedance, then you should also not put them too close to the trace
(at least 5x tracewidth distance) or else you will see ripples in the Impedance
profile.
The distance between two adjacent vias should never be more than 1/10 of the
wavelength of interest to avoid standing waves.
But as I initially pointed out, there is no good reason to use stitching vias
at Mitrostrips, they create a lot of problems and have almost no benefit at all.
BR
Gert
Besuchen Sie uns auf der SPS/IPC/Drives 2014 vom 25. – 27. November 2014 in
Nürnberg, in Halle 10, Stand 140.
http://www.HARTING.de/SPS
----------------------------------------
Absender ist HARTING Electronics GmbH, Marienwerderstraße 3, D-32339 Espelkamp;
Registergericht: Amtsgericht Bad Oeynhausen; Register-Nr.: HRB 8808;
Vertretungsberechtigte Geschäftsführer: Dipl.-Kfm. Edgar-Peter Düning,
Dipl.-Ing. Torsten Ratzmann, Dipl.-Wirtschaftsing. Ralf Martin Klein
-----Ursprüngliche Nachricht-----
Von: Longjun Zhou(LUXSHARE-ICT) [mailto:Longjun.Zhou@xxxxxxxxxxxxxxxx]
Gesendet: Donnerstag, 27. November 2014 01:27
An: Havermann, Gert; si-list@xxxxxxxxxxxxx
Betreff: 答复: [SI-LIST] AW: AW: Re: AW: Shielding vias around microstrip
Hi Gert,
Thank you for your so detailed explanation! One more thing, what rules
I must follow If I have to use stitching vias. I mean how to determine the gap
of two vias in line and the distance between the vias and the signal trace.
Zhou Longjun 周龙军
EE Team / Enterprise Business Group
LUXSHARE-ICT Precision Industry Co., Ltd.
T：+86 769 89089000 Ext 86024 M：+86 13620065253
E：Longjun.zhou@xxxxxxxxxxxxxxxx
A：No. 17 KuiQing Road, QingHuang Industrial Zone, QingXi Town, DongGuan City,
GuangDong, China
-----邮件原件-----
发件人: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] 代表
Havermann, Gert
发送时间: 2014年11月27日 0:35
收件人: si-list@xxxxxxxxxxxxx
主题: [SI-LIST] AW: AW: Re: AW: Shielding vias around microstrip
Those designs with vias are very often just done based on "rules of Thumb". If
you deeply look into the performance differences, you would never do that in a
series Product, but some people still think it has some benefit, and thus they
use such designs in Evaluation Boards where they need "every single bit of
Performance". Most of these boards already lack of a goor Connector to trace
transition, thus you immediately see that the PCB Designer was no SI-Specialist.
The best Trace geometry (I prefer the phrase "impedance Cell" as it includes
the Material and Stack-up) has to be selected for the final Application. If you
are stuck with a very low Layer count, Stripline might not be feasible. If you
can not afford to use a solig GND Plane underneath the signal traces, then
coplanar coupled traces might be of benefit. If you need high isolation and
have a dense Design, then Stripline is the way to go. Tight impedance control
also asks for Stripline. If you have a short chip to chip connection on the
same component Layer, then Microstrip can have great performance because you
don't need to switch Layers.
So as you see, there are many good reasons to pick certain Impedance cells.
Learn about the differences and pros and cons, and you will be able to make the
right choice for each of your designs.
BR
Gert
Besuchen Sie uns auf der SPS/IPC/Drives 2014 vom 25. – 27. November 2014 in
Nürnberg, in Halle 10, Stand 140.
http://www.HARTING.de/SPS
----------------------------------------
Absender ist HARTING Electronics GmbH, Marienwerderstraße 3, D-32339 Espelkamp;
Registergericht: Amtsgericht Bad Oeynhausen; Register-Nr.: HRB 8808;
Vertretungsberechtigte Geschäftsführer: Dipl.-Kfm. Edgar-Peter Düning,
Dipl.-Ing. Torsten Ratzmann, Dipl.-Wirtschaftsing. Ralf Martin Klein
-----Ursprüngliche Nachricht-----
Von: Longjun Zhou(LUXSHARE-ICT) [mailto:Longjun.Zhou@xxxxxxxxxxxxxxxx]
Gesendet: Mittwoch, 26. November 2014 15:09
An: Havermann, Gert; afu@xxxxxxxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Betreff: 答复: [SI-LIST] AW: Re: AW: Shielding vias around microstrip
So what purpose is the vias for? how to design it? I noticed the microstrip
with vias has copper plane on the PCB surface and the one without vias hasn't
the copper plane on trace layer.
Zhou Longjun 周龙军
EE Team / Enterprise Business Group
LUXSHARE-ICT Precision Industry Co., Ltd.
T：+86 769 89089000 Ext 86024 M：+86 13620065253
E：Longjun.zhou@xxxxxxxxxxxxxxxx
A：No. 17 KuiQing Road, QingHuang Industrial Zone, QingXi Town, DongGuan City,
GuangDong, China
-----邮件原件-----
发件人: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] 代表
Havermann, Gert
发送时间: 2014年11月26日 20:53
收件人: afu@xxxxxxxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
主题: [SI-LIST] AW: Re: AW: Shielding vias around microstrip
You are correct.
Stripline is always the best choice, but often Microstrip is cheaper.
Stripline already gives you good isolation when the traces are 5 tracewidths
and more apart, while in Microstrip the Fields are larger and often
10xtracewidth and more is needed for decent isolation. That’s also the reason
why the vias don't really shield because most of the Field is in open space and
do not even see the vias.
BR
Gert
Besuchen Sie uns auf der SPS/IPC/Drives 2014 vom 25. – 27. November 2014 in
Nürnberg, in Halle 10, Stand 140.
http://www.HARTING.de/SPS
----------------------------------------
Absender ist HARTING Electronics GmbH, Marienwerderstraße 3, D-32339 Espelkamp;
Registergericht: Amtsgericht Bad Oeynhausen; Register-Nr.: HRB 8808;
Vertretungsberechtigte Geschäftsführer: Dipl.-Kfm. Edgar-Peter Düning,
Dipl.-Ing. Torsten Ratzmann, Dipl.-Wirtschaftsing. Ralf Martin Klein
-----Ursprüngliche Nachricht-----
Von: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] Im
Auftrag von hws
Gesendet: Mittwoch, 26. November 2014 13:41
An: si-list@xxxxxxxxxxxxx
Betreff: [SI-LIST] Re: AW: Shielding vias around microstrip
Hello Gert,
am I wrong to recomend going from Microstrip to Stripline ?
If shielding is a real need .... ?
Herbert
Am 26-11-2014 12:23, schrieb Havermann, Gert:
> Dear Longjun Zhou,
> the message came in messy so I don't know the exact question. You can try
> again and change the mail format to "text only". sometimes that helps.
>
> regarding stitching vias around Microstrop I can say that these do not really
> shield. The crosstalk to other traces will not be significantly reduces by
> adding these vias. I addition, the space between the vias can act as a filter
> and give your microstrip a very narrow stop-band (depending on distance and
> frequency).
>
> I prefer not to use stitching vias around traces, and even guard traces can
> generate more problems than they claimed to solve.
>
> BR
> Gert
>
>
> Besuchen Sie uns auf der SPS/IPC/Drives 2014 vom 25. – 27. November 2014 in
> Nürnberg, in Halle 10, Stand 140.
> http://www.HARTING.de/SPS
>
>
> ----------------------------------------
> Absender ist HARTING Electronics GmbH, Marienwerderstraße 3, D-32339
> Espelkamp; Registergericht: Amtsgericht Bad Oeynhausen; Register-Nr.: HRB
> 8808; Vertretungsberechtigte Geschäftsführer: Dipl.-Kfm. Edgar-Peter Düning,
> Dipl.-Ing. Torsten Ratzmann, Dipl.-Wirtschaftsing. Ralf Martin Klein
>
> -----Ursprüngliche Nachricht-----
> Von: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] Im
> Auftrag von Longjun Zhou(LUXSHARE-ICT)
> Gesendet: Mittwoch, 26. November 2014 13:11
> An: si-list@xxxxxxxxxxxxx
> Betreff: [SI-LIST] Shielding vias around microstrip
>
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