[SI-LIST] Re: AW: AW: AW: Stripline reference
- From: Robert Haller <rhaller@xxxxxxxxxxxxx>
- To: jeff.loyer@xxxxxxxxx, Stephen.Greenhalgh@xxxxxxxxxxxxxx, si-list@xxxxxxxxxxxxx
- Date: Wed, 2 Oct 2013 13:03:09 -0400
I too have seen the same problem you described when a designer accidently
referenced a high speed signal to 12V . Havoc ensued, and when we measured
the signal to ground could see the 12V power noise being induced onto the
high speed signal. I did debug another case where a differential clock was
referenced to a 3.3V plane that was not closely coupled to ground, and
there were no decoupling caps in the area of the signal destination. The
two interesting things I measured was the differential signal looked fine,
but measureing the clock single ended referenced to ground show the 3.3V
noise coupled onto the signal. The second part of this was the coupling
was spatial. i.e. near the driver (where there was adequate decoupling)
the single ended signal looked good, but at the end of the line near the
received the coupling was significant enough (again measuring single
ended) to cause errors.
Bob
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Loyer, Jeff
Sent: Wednesday, October 02, 2013 12:53 PM
To: Stephen.Greenhalgh@xxxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: AW: AW: AW: Stripline reference
Here's my experience to-date...
For the stackups I've dealt with, "ground" and "power" planes on the PCB
have such low impedance between them that they are essentially the same
for high speed signaling reference. I.E., if you TDR between them, it
indicates a dead short. Similarly, if you TDR a stripline trace that lies
between a ground and power plane, it doesn't matter which you choose as
reference (or had them shorted together at the launch) - the
TDR/TDT/crosstalk waveforms are identical. Even when I had microstrip
traces, some of which were referenced to power and others which were
referenced to ground, I could not discern any significant difference in
the TDR waveforms whether I chose power or ground as reference (FEXT was
increased slightly, and odd-even mode TDT showed slightly more
difference). This was true for bare boards; the decoupling caps weren't
in play.
This is true for the designs I've investigated for this phenomenon,
perhaps there are other designs/stackups which would have different
results.
On the other hand, I have experienced problems having signals referenced
to a power plane for a different reason. The noise on the power plane has
gotten injected into my signals and caused severe problems. Of course
that noise is going to be dependent on the power plane itself (12V power
might kill a signal while 1.8V power might work fine).
Differential signals have proven to be more immune to this noise but,
interestingly enough, I've had noise on a differential clock signal wreak
havoc. We believe that the "signals" themselves weren't the problem, that
the noise on those signals got coupled into the chip and caused problems,
but that's only conjecture.
Jeff Loyer
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Stephen Greenhalgh
Sent: Wednesday, October 02, 2013 8:18 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: AW: AW: AW: Stripline reference
I think this message is sufficiently on-topic not to be regarded as
hijacking the thread. I offer my apologies in advance if others disagree.
Clearly simulation must reflect the actual pcb as closely as possible, and
whichever plane is reference in the pcb should be used in the simulation.
But, in the pcb, as far as signal integrity is concerned which (power or
ground) is the better reference plane to use? Does it matter hugely for
differential (as opposed to single-ended) signalling? Does it depend on
the technology used?
For example, a LVPECL output stage typically has a constant current source
connected to power with the switching transistors between this and ground.
Data sheets define the voltage levels relative to ground. Terminations
connect between signals and ground. So ground is the obvious reference
plane to use.
However, for CML the reverse is the case. The constant current source is
connected to ground with the switching transistors between this and power.
Data sheets define the voltage levels relative to power. Terminations
connect between signals and power. So, is power the better choice for
reference plane?
Just as importantly, why (or why not)?
Regards,
Stephen
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Scott McMorrow
Sent: 02 October 2013 12:51
To: steve weir
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: AW: AW: AW: Stripline reference
Amit
For a power referenced differential pair, all the "bad" stuff happens in
two places.
1) getting from the package onto the power plane reference
2) getting off the power plane reference and onto the outbound connector.
Shorting the to ground is not even close to an approximation of this. If
you want to model this, you have to go back into the package and to the
other side of the connector where there are grounds referencing the
signal.
However (spoiler alert) your power referenced differential pair is an
resonance and EMI nightmare. You might want to figure out how to engineer
it out.
We often talk about not routing over split planes. Well, your
differential pair crosses two splits, one coming off the package, and one
jumping onto the connector.
good luck
Scott
On Wed, Oct 2, 2013 at 5:00 AM, steve weir <weirsi@xxxxxxxxxx> wrote:
> Amit, no that is a bad idea. Unless the geometries are small compared
> to the signal wavelengths such an approximation will be poor.
>
> Steve.
> On 10/2/2013 1:16 AM, Amit Kumar wrote:
> > Hi Gert,
> >
> > I messed up the question actually.
> > I want to know the impact of shorting the vdd and gnd nets. The
> > TX/RX
> model I have is a behavioural model which does not take power into
account.
> > So the conventional port reference definition of dual referencing
> > will
> not work for me.
> > So I was thinking whether it is ok to short vdd and gnd nets for
> > signal
> s parameter extraction?
> > One problem which is obvious is that ill be ignoring the inductance
> which the return path would have encountered for travelling from vdd
> to gnd. Will shorting vdd gnd locally on one end give me an approximate
result?
> >
> >
> > Regards
> > Amit Kumar
> >
> > Baghmane Tech park, Bengaluru
> > T: + 91-80-42422526
> > amit.kumar@xxxxxxxxxxx
> >
> >
> > -----Original Message-----
> > From: si-list-bounce@xxxxxxxxxxxxx
> > [mailto:si-list-bounce@xxxxxxxxxxxxx]
> On Behalf Of Havermann, Gert
> > Sent: Wednesday, October 02, 2013 1:27 PM
> > To: si-list@xxxxxxxxxxxxx
> > Subject: [SI-LIST] AW: AW: AW: Stripline reference
> >
> > Hi Amit,
> >
> > it is NEVER ok to use power as a port reference in simulation
> > unless,
> the later Chip also uses power as reference (which I haven't seen in
> high speed digital yet).
> > The Pots have to be placed "close to reality". If Your chip has a
> > GND
> reference for signal output and you change layers in the fanout of the
> package, then your port has to be placed on the Solder Land (Chip
> Footprint) referencing to GND. The Power plane which is reference for
> the trace on the new routing Layer will automatically become reference
> to the signal that is routed in close proximity. If you then don't
> provide some sort of return path for ac-return currents from Power
> plane to your Ports GND reference, you will see massive ringing and
> radiation, and this ringing will also be seen in reality if the return
path is missing.
> > If you would use PWR as the Port reference, you will not see the
> > ringing
> that will be there in reality.
> >
> > Always remember: Simulation can be a bitch as Simulation will always
> give you a result, but never tells you if the result is true or wrong.
> It is on you to model as close to reality as possible. If you decide
> to drop features in simulation, YOU have to make sure that the result
> is still usable.
> >
> > BR
> > Gert
> >
> >
> > ----------------------------------------
> > Absender ist HARTING Electronics GmbH, Marienwerderstraße 3, D-32339
> Espelkamp; Registergericht: Amtsgericht Bad Oeynhausen; Register-Nr.:
> HRB 8808; Vertretungsberechtige Geschäftsführer: Dipl.-Kfm.
> Edgar-Peter Düning, Dipl.-Ing. Torsten Ratzmann
> >
> > -----Ursprüngliche Nachricht-----
> > Von: Amit Kumar [mailto:Amit.Kumar@xxxxxxxxxxx]
> > Gesendet: Mittwoch, 2. Oktober 2013 07:09
> > An: Havermann, Gert; si-list@xxxxxxxxxxxxx
> > Betreff: RE: [SI-LIST] AW: AW: Stripline reference
> >
> > Hello Gert/Experts,
> >
> > The discussion on the stripline reference was really good. Thanks to
> everyone for the contribution.
> >
> > I have a differential pair routed on top and bottom layer(so both
> microstrip). The top layer routing has a vdd plane as reference and
> the bottom routing has gnd as reference.
> > I have two questions here:
> >
> > 1) Do you see a significant impact on performance because of
> > different
> reference plane on different layers.
> > 2) How do we assign ports for this differential pair? Is it ok to
> > assign
> one side port with ground reference and other side with power reference?
> >
> > Regards
> > Amit Kumar
> >
> > Baghmane Tech park, Bengaluru
> > T: + 91-80-42422526
> > amit.kumar@xxxxxxxxxxx
> >
> >
> > -----Original Message-----
> > From: si-list-bounce@xxxxxxxxxxxxx
> > [mailto:si-list-bounce@xxxxxxxxxxxxx]
> On Behalf Of Havermann, Gert
> > Sent: Monday, September 30, 2013 1:31 PM
> > To: si-list@xxxxxxxxxxxxx
> > Subject: [SI-LIST] AW: AW: Stripline reference
> >
> > Amit,
> >
> > if power and GND have the same distance to the trace, then both will
> > see
> identical coupling and the return current that flows on the Planes
> will be equal in both planes.
> > The Cap I mentioned is the coupling cap between Power and GND. The
> Return current on the Power plane has to go back to the signal source.
> Since the Power plane has no direct DC connection to GND, you have to
> establish a capacitive coupling to allow the current to flow back to
GND.
> The position of these caps governs the "detour" you force the return
> current to flow. This means additional inductance in your path, and a
> great source of crosstalk. Without Coupling caps you will create lots
> of radiation as the currents will find their way "over the air".
> >
> > I hope this helps.
> >
> > BR
> > Gert
> >
> >
> > ----------------------------------------
> > Absender ist HARTING Electronics GmbH, Marienwerderstraße 3, D-32339
> Espelkamp; Registergericht: Amtsgericht Bad Oeynhausen; Register-Nr.:
> HRB 8808; Vertretungsberechtige Geschäftsführer: Dipl.-Kfm.
> Edgar-Peter Düning, Dipl.-Ing. Torsten Ratzmann
> >
> > -----Ursprüngliche Nachricht-----
> > Von: Amit Kumar [mailto:Amit.Kumar@xxxxxxxxxxx]
> > Gesendet: Freitag, 27. September 2013 13:20
> > An: Havermann, Gert; si-list@xxxxxxxxxxxxx
> > Betreff: RE: [SI-LIST] AW: Stripline reference
> >
> > Hello Gert,
> >
> > What if power and ground layers are equidistant from the signal layer?
> > Also, can you explain what do you mean by the position of the cap?
> >
> > Regards
> > Amit Kumar
> >
> > Baghmane Tech park, Bengaluru
> > T: + 91-80-42422526
> > amit.kumar@xxxxxxxxxxx
> >
> > -----Original Message-----
> > From: si-list-bounce@xxxxxxxxxxxxx
> > [mailto:si-list-bounce@xxxxxxxxxxxxx]
> On Behalf Of Havermann, Gert
> > Sent: Friday, September 27, 2013 4:37 PM
> > To: si-list@xxxxxxxxxxxxx
> > Subject: [SI-LIST] AW: Stripline reference
> >
> > It all depends on the position of Coupling caps, the distance to
> > each
> plane and the speed of your signal.
> > If you simulate, you have to take the position of the caps into
> > account,
> or at least leave the power plane floating at each port. The model
> must be as close to reality as possible, thus only connections between
> planes that are really there should be used in simulation. And the
> right boundary has to be used as it has massive influence on the
results.
> >
> > BR
> > Gert
> >
> >
> > ----------------------------------------
> > Absender ist HARTING Electronics GmbH, Marienwerderstraße 3, D-32339
> Espelkamp; Registergericht: Amtsgericht Bad Oeynhausen; Register-Nr.:
> HRB 8808; Vertretungsberechtige Geschäftsführer: Dipl.-Kfm.
> Edgar-Peter Düning, Dipl.-Ing. Torsten Ratzmann
> >
> > -----Ursprüngliche Nachricht-----
> > Von: si-list-bounce@xxxxxxxxxxxxx
> > [mailto:si-list-bounce@xxxxxxxxxxxxx]
> Im Auftrag von Jason wuc
> > Gesendet: Freitag, 27. September 2013 12:55
> > An: si-list@xxxxxxxxxxxxx
> > Betreff: [SI-LIST] Stripline reference
> >
> > Hello Experts,
> > I need your help.
> >
> > I am extracting s-parameter of some strupline traces. These traces
> connect two flip chips on board and are routed between power and
> ground plane where power is upper plane and ground is lower plane I
> am in doubt that whether I should take ground/power as reference or
> both planes as reference while assigning ports.
> >
> > Please reply.
> >
> > Jason
> >
> >
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