Hi Suresh,
making the antipad bigger increases inductance of the trace because the GND
Reference is missing inside the antipad. Use bigger traces in the void area, or
keep the antipad of the signals reference planes small.
And keep in mind: most of the capacitive impedance peak is caused by the via
stub and is not the "real impedance". Simulate without any stub first to find
the impedance of the via structure, and then add via stublength to examine its
effect.
BR
Gert
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-----Ursprüngliche Nachricht-----
Von: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] Im
Auftrag von Suresh Kumar
Gesendet: Donnerstag, 16. April 2015 09:29
An: <si-list@xxxxxxxxxxxxx>
Betreff: [SI-LIST] 100ohm via model
Hi Experts,
I'm designing a 100 ohm via model with 5% tolerance for 15 gbps lane (260mil
thick board ) For this , I'm sweeping till 50Ghz using HFSS.
But when i see the TDR with 20psec (0.30*UI) , I'm getting capacitive at
0-50psec and inductive peak at 75-100psec...
when I try to optimize it by changing the antipad and signal to signal via and
signal to gnd via distance, the whole curve is being shifted to high impedance
or low impedance
Please advise how can I identify the exact location of these C and L changes ?
If i calculated using 6"/1ns , the C & L is falling very near which is is in
the via area ...
Plz help me on this and suggest....
THANKS
Suresh
Sent from my iPhone 5s
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