[SI-LIST] Re: ADC layout: moving from PCB to chip
- From: steve weir <weirsi@xxxxxxxxxx>
- To: leeritchey@xxxxxxxxxxxxx,"Philip Zimmermann" <paz@xxxxxxxxxxx>, si-list@xxxxxxxxxxxxx
- Date: Mon, 17 Jul 2006 09:43:42 -0700
Lee, I will provide you with two examples:
1) In industrial controls where the sensitive part is on the digital
side and the noise offender is the high power drive circuits.
2) IC w/ APLL and not much else analog. This includes many Freescale
processors. Freescale has long had the good sense to avoid the
ferrite bead peaking problem by using resistors for the series impedance.
For an experiment, we should be able to take a FS processor board and
demonstrate this effect by writing some test code to make the busses
light up, and observing clock jitter with and without the APLL
Vdd/Vss network inserted / bypassed.
There is enough misinformation circulating that it is not surprising
that you would not have encountered students able to understand and
articulate the subtleties of a difficult subject. After all they
have come to learn from you.
In the end it all comes down to numbers and when we jam a filter in
someplace which is what we are doing to Vss, we need to make certain
that we satisfy both S21 and S11. S11 is often overlooked. I think
this is a point you make frequently and one I agree with. A lot of
application notes tell people to hack up their Vss making S11 a
disaster. That is something I wish were fixed yesterday.
I think that anyone who makes an assertion has an obligation to be
able to back it. The broader the assertion the more thorough the
backing should be. I am more than willing to try and find an example
and test protocol that we can agree upon. Time is the difficult
problem right now.
I've gotta dash down the 101 right now, but we can pick this up in
more detail later with drawings for show and tell.
Regards,
Steve
At 08:14 AM 7/17/2006, Lee Ritchey wrote:
>Steve,
>
>I keep hearing about there being exceptions. As you know, I teach a design
>class several times a year. To date, that has included almost 6000
>engineers and designers. In each class this topic comes up. Each time I
>ask if anyone has an example of a design being made to perform better by
>having these two grounds. So far, there has not been a single case
>presented that demonstrates this. There have been may cases where putting
>the grounds back together makes things better.
>
>I'm still waiting for that case where things get better. When I find it,
>I'll include it in my classes and in my next book.
>
>Til then, I stand by my earlier statements.
>
>It does rest with the proponent of multiple grounds to prove that it is a
>good idea, not the other way around.
>
>
> > [Original Message]
> > From: steve weir <weirsi@xxxxxxxxxx>
> > To: <leeritchey@xxxxxxxxxxxxx>; Philip Zimmermann <paz@xxxxxxxxxxx>;
><si-list@xxxxxxxxxxxxx>
> > Date: 7/16/2006 10:25:58 PM
> > Subject: Re: [SI-LIST] Re: ADC layout: moving from PCB to chip
> >
> > Lee, that is usually true. But like most things we need to be
> > careful, because there are definitely exceptions. I think the
> > biggest mistake that people make looking at low pass noise filters is
> > looking at S21 only and losing sight of S11. As always it pays to
> > crank through the numbers. Getting the information to do that
> > properly can sometimes be exasperatingly difficult.
> >
> > Regards,
> >
> >
> > Steve.
> >
> > At 05:36 PM 7/16/2006, Lee Ritchey wrote:
> > >Philip,
> > >
> > >No doubt you saw applications notes making such statements. If you saw
>one
> > >of the rarely asked quesitons from James Bryant who is one of ADs
>technical
> > >specialists, he says "When a data sheet tells you to do this it is
> > >incorrect and you should ignore it." Two separate grounds on the PCB has
> > >always been incorrect. WOnder how long it will take to get this wrong
> > >concept flushed out of our profession.
> > >
> > >
> > > > [Original Message]
> > > > From: Philip Zimmermann <paz@xxxxxxxxxxx>
> > > > To: <si-list@xxxxxxxxxxxxx>
> > > > Date: 7/16/2006 5:43:02 AM
> > > > Subject: [SI-LIST] ADC layout: moving from PCB to chip
> > > >
> > > > I recall seeing layouts of eval boards from Analog Devices and others
>that
> > > > used separate ground planes underneath the analog and digital
>sections of
> > > > the printed circuit board, with a slim trace connecting the two ground
> > > > planes. There were a few reasons given for doing this at the time,
>and the
> > > > technique apparently worked out better for those designs.
> > > >
> > > > As a design shrinks from a PCB to a chip, it becomes less practical to
> > > > consider a ground plane underneath one part of the circuit, and the
> > > > physical proximity of the two circuit regions makes one wonder to what
> > > > extent the two sections can be isolated for the benefit of noise
>reduction
> > > > (less digital noise generated by the digital section being captured
>by the
> > > > analog section) and signal integrity.
> > > >
> > > > Also, since the power supply voltages have dropped to about 1V, have
>the
> > > > chip designers concerned with wringing out best performance decided to
> > > > place less emphasis on layout, gound return paths, etc.?
> > > >
> > > > I am moving from the PCB world to the chip design world and need to
>tweak
> > > > my mind-set accordingly.
> > > >
> > > > Thanks.
> > > > -- paz.
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