[SI-LIST] ADC Gnd Noise
- From: deepak kamath <kd_kamath@xxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Tue, 10 Apr 2007 22:37:14 -0700 (PDT)
Hi,
I have designed a signal processing board to sample thermal sensor data,
process data and display images. The sensor has the sensitivity of 20mV and an
ADC (Analog Devices, AD9240,14-bits) is used to sample the analog signal from
the sensor. ADC has 5 volt analog and digital supply with analog and digital
grounds. The sensitivity of the ADC is 0.3mV per bit and is configured for
positive single ended mode of operation with input dynamic range of 5 volts.
The board also has FPGA and DSP which are used to process the sensor signal.
The clocks used are 100MHz to drive FPGA & DSP with ADC operating at 10MHz.
The required power generation of 5 volts, 3.3 volts and 1.2 volts
are done using switching regulators and are mounted on a separate board called
power supply board. From power supply board power is given to signal processing
board. The received powers in signal processign board are porperly filtered and
converted into power planes of 5 volts, 3.3 volts and 1.2 volts. Similarly
analog and digital grounds are etched out in a single ground plane and are
connected via ferrite bead.
The problem we are facing is a noise of 80mV(p-p) is observed on
analog ground, digital ground, analog 5 vots supply and digital 5 volts supply
at the ADC pins. This noise is corrupting sensor signal. ADC?s LSB 6 bits are
toggeling even when no signal is applied to ADC. The signal processing board
constitutes of 12 layers and following layer stack is followed.
1. Top signal layer
2. Ground Plane layer
3. Power plane layer
4. Signal layer
5. Signal layer
6. Signal layer
7. Signal layer
8. Signal layer
9. Signal layer
10. Power layer
11. Ground layer
12. Bottom signal layer
Please suggest me ways to reduce ground and power noise.
Regards
Deepak
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