[SI-LIST] ADC GND Noise

  • From: deepak kamath <kd_kamath@xxxxxxxxx>
  • To: si-list@xxxxxxxxxxxxx
  • Date: Thu, 12 Apr 2007 23:26:09 -0700 (PDT)

 Hi,

 Thanks for suggestions.

We have used Tektronix scope of 5GHz sampling with 500MHz bandwidth

to observe noise on the planes.The sensor video output is passed to an OPAMP 
whose output is then given to ADC. The OPAMP is selected to cater for sensors 
output impedence  and ADC input impedence. Also capacitive loading of ADC is 
well managed. We have not observed any dip in the video signal at the input of 
ADC  at the time of sampling.

 

We have used the differential ADC in single ended mode of operation

to cater for the dynamic range ( 0 to 5 Volts of sensor video) of 

the  input signal. The VinB pin of ADC is connected to VREF(2.5V 

generated  by the ADC itself) and VinA pin is fed with sensor signal. 

 

The following experiments were done:

1. When the sensor was not connected to VinA pin of ADC, ADC itself

generated 2.5V on VinA pin. The VinB pin of ADC is connected to VREF

(2.5V internally generated from 5V supply to ADC). The expected 

14bit output was 0x2000, but observed output was anywhere between 0x2080  to 
0x20FF. 

2. A constant voltage of 2.5V from external source was applied to 

VinA  pin of ADC. The expected output was again 0x2000, but suprprisengly  all 
14 bits from the ADC were observed to be toggling.

 

The above two observations indicate noisy 5V suplly to ADC. The 

Noise  spectrum of the supply voltage to ADC was seen to be peaking at 7.5  MHz 
which is the ADC samplig clock. Also, 15MHz is a clock given to  sensor. 

 

The following routing information might help us to solve the 

problem. The clock to the ADC is routed in the layer (layer 9) which is just  
above the power plane layer (layer 10). Layer 10 consists of power  plane of 
3.3V and 1.2V which are not related to ADC as it operates  at analog 5V. 

 

 As most of the responses are towards a change in the layer stackup,

 the following layer stackup is planned for the redesign

 

 Layer 1 Mounting pads and minimal routing to vias (TOP Layer)

 Layer 2 a Split Ground plane (AGND and DGND). These two plane are 

Connected under ADC with a copper of 1 oz and of 2-3 mm width and FR4  board  
material.  ADC to be place above AGND. 

 Layer 3 à Signal (Horizontal Routing). Route all signal between ADC

 and FPGA in this layer. Also other signals may be routed

 

 Layer 4  Signal (Vertical Routing)

 Layer 5 Power Plane (Split Plane of AVDD5, VDD5, VDD3_3 and 

VDD1_2)

 Layer 6 Signal (Horizontal Routing)

 Layer 7  Signal (Vertical Routing). 

 Layer 8  Ground plane (DGND).

 Layer 9  Signal (Horizontal Routing). All Clocks like FPGA_CLOCK,

 CLOCK, CLOCK_BIRD, DSP_CLK, PPI_CLK, SRAM1_CLK, SRAM2_CLK, 

SERIAL_CLK  along with other signals. All clocks should be as far away as 
possible  among themselves and other signals in this layer. Also must have the  
shortest possible path length.

 Layer 10  Signal (Vertical Routing). All signals between FPGA and

 DSP along with other signal routing.

 Layer 11  Power Plane (Split Plane of VDD3_3 and VDDINT_DSP)

 Layer 12  Mounting pads and minimal routing to vias (Bottom 

Layer).

 

 Kindly send us your valuable comments.
   Regards
  Deepak

       
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