[SI-LIST] Re: AC coupling Capacitor
- From: <Cortex.Chen@xxxxxxxxxxxx>
- To: <pchauhan@xxxxxxxxxxx>
- Date: Fri, 26 May 2006 11:00:11 +0800
Hello Prakash,
I also encountered your question about two years ago (when I researched =
Intel Bensley platform...).
I tried to ask any contact windows from Intel, however, there is not any =
response and therefore I turned to review PCI-E interface.
I like to share private thinking for your reference.
Based on ac capacitor's functionality, there is not any difference =
between transmitter and receiver.
So the capacitors may theoretically be placed anywhere along the =
interconnect... =20
In addition, we should meet both spec. of TX and Rx for PCI-E not only =
meets receiver's spec for post interface.
If you have PCI-E spec (rev. 1.1) or/and NOTE1*, please open section =
4.3.3.4 and check the fig. 4-25 (transmitter test load).
You could realize why the ac cap is closer to the transmitter for PCI-E.
Note1: PCI Express* Simulations: Differences between Pin and Pad =
Measurements
In addition, I am also searching some papers to discuss ac cap location =
for gain for SAS interface.
You could check it....
Regards,
Cortex
From: "Chauhan, Prakash" <pchauhan@xxxxxxxxxxx>
Date: Thu May 25 08:37:01 CDT 2006
To: istvan.novak@xxxxxxxxxxx, jain.nitin@xxxxxxxxx, =
si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: AC coupling Capacitor
Hi Istvan,
I have seen design guides that suggest that for Ethernet (Gig-E
and Xaui) the caps should be close to the receiving end while for PCI
express these should be closer to the transmit side (4.75 inch max
suggested in both cases). Both these are 8B/10B encoded, 100 ohm
differential, serial links and it is not clear to me why this should be
different for these two serial interfaces (given that the PCB loss and
impedance discontinuity due to the caps should affect both types of
links in very similar manner). Perhaps it has something to do with the
preemphasis and receive equalization characteristics of the
driver/receiver?! =3D20
--Prakash. =3D20
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of istvan.novak@xxxxxxxxxxx
Sent: Thursday, May 25, 2006 8:10 AM
To: jain.nitin@xxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: AC coupling Capacitor
Nitin,
Regular surface-mount DC-blocking capacitors will create discontinuities
in the differential lines, because most of our traces today are much
narrower than the capacitor pad and body. The typically strongest
discontinuity is the parallel body capacitance to ground. If you use
two capacitors along eachline, you get two discontinuities, so do it
only if there is a strong reason. =3D20
Regarding their location along the lines: as a first-cut approach, their
location should not (and does not) matter, you just want to place the
capacitors on both lines at the same location symmetrically so that mode
conversion is minimized. If you (have to) take a closer look, the
location of the discontinuity along the line may matters somewhat as it
interacts with the losses and non-ideal impedances of the lines and
transmit/receive impedances. If this matters, you need a simulator to
find the answer.
Regards,
Istvan Novak
SUN Microsystems
From: jain.nitin@xxxxxxxxx
Date: Thu May 25 06:03:58 CDT 2006
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] AC coupling Capacitor
Hello,
For a gigabit differential pair AC coupling capacitor is used. But what
exactly is the use of AC coupling capacitors? I believe that they are
used when the bias voltage of driver & receiver are different.=3D3D0D
Also where exactly AC coupling capacitors should be placed when the
differential trace is running on a backplane from one daughter card to
other (at driver end or at receiver end).
What will happen if two AC coupling caps are used. One at driver side
and other at receiver side.
With regards,
Nitin
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