[SI-LIST] Re: AC Specs and SI in an MCP
- From: "Inmyung Song" <imsong@xxxxxxxxxxxxxx>
- To: <aaron@xxxxxxxxxxxxx>, "Si-List (E-mail)" <si-list@xxxxxxxxxxxxx>
- Date: Thu, 24 Jan 2002 09:09:23 +0900
Hello,
I had some experiances about that, I remembered my case was Module Ram which
was
one of the DRAMs.
My simulation flow is below;
1. Mulitiboard Simulation via ICX : This needs the source file of ICX of the
Modules.
Timing Delay : System Net Delays.
Signal Integrity : Probing via ICX
2. EBD Model via ICX : This needs the source file of ICX too, if the Module
vendor doesn't support that.
Timing Delay : Timing Chart via ICX
Signal Integrity : Probing via ICX
3. Common feature
In my case, the female connector's spec had no pin parasitic, then I
used
the No.2's method.
I don't have much information about this and can't explain.
If you have any other question, pls let me know.
Good luck
Inmyung.
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]On
Behalf Of Aaron Frank
Sent: Thursday, January 24, 2002 5:18 AM
To: Si-List (E-mail)
Subject: [SI-LIST] AC Specs and SI in an MCP
Hello All,
I have an application for the development of an IC multi-chip package which
contains a high-speed memory controller ASIC plus internal memory ASICs
(multiple die) interconnected on the substrate. The memory bus also goes to
BGA package pins, and can connect to external expansion memory.
I am concerned about how to specify AC timing specs for the entire device,
as well as how to explain/consider SI issues for the internal memory.
Depending upon the end user's external connections, the internal memories
may experience reflections and levels which do not guarantee reliable
operation.
>From a topology perspective, the internal memories appear close to the
driver, on short (1") stubs. Alternate interconnects may be possible (ie:
daisy-chain), but still external connections may drive reflections back into
the package, to the driver and the internal memories.
Signal Integrity Concerns
=========================
The purist approach would be to provide IBIS EBD models of the package,
along with IBIS models of the bare dies, and have the end customer verify SI
and timing to the internal memories as well as external memories. However,
real world dictates that not all customers would be as diligent.
Are there any accepted practices or methods to specify signal quality
concerns for a package pin which is effectively in the middle of a
high-speed bus?
AC Timing
=========
AC timing from the memory controller can be easily specified at the package
pin, but typically is only considered for setup/hold margins at an external
device. How can I specify requirements for internal memory devices?
Q: Has anybody had a similar issue in an MCP (or equivalent) environment?
Q: As a designer, what would you do to verify/validate your design (timing &
SI):
a) as a 1st order approximation (ie: not heavily modeled and simulated)?
b) in full simulation?
Any and all comments/suggestions are greatly appreciated.
AAron
*************************************
Aaron Frank, P.Eng.
SiberCore Technologies
email: aaron@xxxxxxxxxxxxx
*************************************
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