[SI-LIST] Re: AC Blocking capacitor relative positions and reference plane voids
- From: "Lee Ritchey" <leeritchey@xxxxxxxxxxxxx>
- To: "jean-francois hasson" <jfhasson@xxxxxxxxxxxxxxxx>, si-list@xxxxxxxxxxxxx
- Date: Wed, 18 Nov 2009 16:39:39 -0800
Jean-Francois,
This is a great deal of work for no detectable benefit. I think someone
made that rule up. Don't bother making these voids. Their effect on the
overall impedance is nearly undetectable. I know, I've made the
measurements. I'll bet the author of the rule hasn't.
Lee Ritchey
> [Original Message]
> From: jean-francois hasson <jfhasson@xxxxxxxxxxxxxxxx>
> To: <si-list@xxxxxxxxxxxxx>
> Date: 11/18/2009 3:06:49 PM
> Subject: [SI-LIST] AC Blocking capacitor relative positions and reference
plane voids
>
> Hi,
>
> When looking at AC coupling capacitors on high speed serial links it is
> often recommended to void the reference plane under these capacitors to
> minimize capacitance variations. Most of the times, in the designs I
> have seen, the void is exactly underneath each AC blocking capacitor
> including landing pads. If ever the capacitors were quite close, would
> there be any reason why a single void below both capacitors would be an
> issue ? I have also noticed that most of the times AC blocking
> capacitors are not as close as possible to a transmitter or receiver
> where I thought it was beneficial to do so to remove the number of
> impedance disruptions ? Could anyone provide me with some explanation ?
>
> Best regards,
>
> JF
>
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