[SI-LIST] A high-speed I/O engineer/specialist job opening in Altera
- From: Mike Peng Li <mpli@xxxxxxxxxx>
- To: "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
- Date: Fri, 15 Apr 2011 17:53:14 -0700
Hello:
Altera (Nasdaq:
ALTR<http://search.yahoo.com/r/_ylt oGdSCIRKdNKzMAdyhXNyoA/SIGttl4h3t/EXP02829288/**http%3a/finance.yahoo.com/q%3fs=ALTR%26d=t>,
Altera Corporation designs, manufactures and markets a broad range of
high-performance high-density programmable logic devices (PLDs) and associated
development tools ...
www.altera.com<http://www.altera.com>), a world leading FPGA company, currently
has the following position open in high-speed I/O R&D at its San Jose, CA
location.
(http://tbe.taleo.net/NA3/ats/careers/requisition.jsp?org=ALTERA&cws=1&rid57)
If you are interested in this position, and feel that you are qualified, please
send your resume directly to me.
Thanks !
Mike
________________________________
Senior Level High-Speed Specialist
Location:
US-CA-San Jose
Requisition ID:
1057
# of openings:
1
________________________________
Description
As a Senior Level High-Speed Specialist in Product Engineering, you are
expected to conduct leading edge R&D projects in various sub areas of HSIO,
including architecture, performance critical components, link modeling,
simulation, and analysis, time and frequency design characterization and
verification with various types of lab equipments. Your primary focus will be
on developing leading edge electro-optical HSIO simulation/modeling
technologies/products with different abstractions, from transistor, to
integrated circuit, to behavior/algorithmic. You are expected to interact with
various functional groups related to HSIO technology and product to initiate,
drive, and deliver the R&D projects/products in a timely manner. You are also
expected to write technical papers, patent applications based on the outcomes
of the R&D projects. You are expected to be an independent, a self-starter, a
team-player, with minimum supervision.
The successful candidate's minimum qualifications will include the following:
* BS/BE in Electrical Engineering, Physics, or equivalent with a
minimum of 12 years postgraduate and relevant experiences in the semiconductor,
EDA, communication , or computer industry.
* In depth experiences and/or knowledge on modern electro-optical HSIO
architecture, signaling, clock generation, recovery, and distribution,
equalization, data driving and data recovering.
* In depth experiences and/or knowledge on transistor/gate/circuit
level design of transmitter, receiver, SERDES, PLL, DLL, oscillator ICs and
devices.
* In depth experiences and/or knowledge on HSIO signaling theorem,
modeling, simulation, analysis, and debug for HSIO links and subcomponents,
jitter, signal integrity, power integrity.
* In depth experiences and/or knowledge on design verification,
characterization and debug methodologies for HSIO devices and systems,
signaling, AC, DC, and timing parametrics, and jitter, signal integrity, power
integrity.
* Experiences and solid coding capabilities in C/C++ is a must.
* Experience and/or familiarity with high-speed I/O standards such as:
PCIE, HyperTransport, SATA, Fibre Channel, Gigabit Ethernet, XAUI, GigE,
CEI/OIF, SONET, DDR2, DDR3. The emphasis is on the PHY specifications.
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