[SI-LIST] Re: A Question about Target Impedance Threshold computation
- From: "Dhamija, Naresh" <Naresh.Dhamija@xxxxxxx>
- To: steve weir <weirsi@xxxxxxxxxx>
- Date: Mon, 1 Jul 2013 12:06:16 +0530
Thanks Steve,
Can you elaborate on term "symmetry" here.
Regards
Naresh
-----Original Message-----
From: steve weir [mailto:weirsi@xxxxxxxxxx]
Sent: Monday, July 01, 2013 12:04 PM
To: Dhamija, Naresh
Cc: larrys@xxxxxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: Re: [SI-LIST] Re: A Question about Target Impedance Threshold
computation
Problems like this require viewing the distributed currents and impedance. A
single scalar value is not suitable. Usually, to make the problem easier to
analyze we apply symmetry wherever possible.
Steve
On 6/30/2013 11:26 PM, Dhamija, Naresh wrote:
> Hi Larry,
>
> Your explanation for reducing the target impedance spec. for different clock
> systems on a chip is too good especially for resonant points. But I have more
> severe problem here:
>
> What if all are on same clock like a DDR bus where more than 72 IOs can
> switch at a time at linearly adding the currents from each IO puts the target
> impedance spec. to a very low value and at resonance point that is very hard
> to meet.
> Can you comment on such situation - how target impedance should be calculated.
>
> Regards
> Naresh
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of Smith, Larry
> Sent: Monday, July 01, 2013 10:28 AM
> To: weirsi@xxxxxxxxxx; si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: A Question about Target Impedance Threshold
> computation
>
> Hi all, just catching up on some back email here.. The target impedance
> concept can be applied at many levels of assembly.
>
> If there are several identical power consuming chips on the PCB, a target
> impedance can be calculated according to the sum of the current consumed by
> each of them. It is highly likely that all of them will draw DC current at
> the same time so the DC target impedance needs to take into account the
> maximum DC current of each device.
>
> At low frequency, it is possible for the several devices to draw current
> transients at the same time so a conservative approach is to linearly add the
> several transient currents when making the target impedance calculation.
> This may be appropriate when sizing the DC VRM and bulk/ceramic capacitors
> that are effective around the 1 MHz frequency band.
>
> As frequency goes up, it is more difficult to meet a conservatively
> calculated target impedance. But it is also more difficult for the several
> current consumers to draw transient current in phase at exactly the same
> time. It is more appropriate to add the transient currents in a statistical
> fashion with an RMS summation rather than linear summation. This essentially
> assumes that the transient currents are statistically independent. My rule
> of thumb is that transient currents from circuits on different clock domains
> are statistically independent. The target impedance calculated by this
> method is easier to meet and is used with minimum risk if the transient
> currents from the several consumers are truly statistically independent.
>
> Then within a single chip, there may be several circuit blocks that draw
> current from the same power rail. The same concept applies here: if the
> circuit blocks are statistically independent (which is most likely the case
> if they are on different clock domains) then their transient currents can be
> RMS'ed together. This is usually a good thing to do at die/package resonant
> frequencies which are often around the 100 MHz band. It is really difficult
> to line up the current transients in time from several independent blocks so
> that they stimulate a 100 MHz resonance in a coherent manor.
>
> Using these concepts, a target impedance for a single chip can be calculated
> statistically from knowledge of circuit blocks drawing current from the
> voltage rail in question. And at the PCB level, transient current drawn by
> several chips can be calculated statistically. This makes the target
> impedance a function of frequency. Steven Ohlsen's comment is correct, "It
> seems that the current portion of the target impedance equation varies from
> point to point on the board depending on a host of very complicated
> relationships." It is really up to the component supplier to provide the
> target impedance for a chip and then for the board designer to combine the
> target impedances for the several chips on the same PCB power rail by adding
> linearly at DC and low frequencies and statistically at higher frequencies.
>
> In summary, it is highly probable that all circuits on the PCB will draw DC
> current at the same time and the VRM must be sized accordingly. But as we
> get up into the 1 MHz, 10 MHz, 100 MHz and 1 GHz bands, the probability of
> drawing transient currents in phase at the same frequency greatly diminishes.
> The target impedance at the different chip locations on the PCB should
> reflect this in different frequency bands.
>
> Regards,
> Larry Smith
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of steve weir
> Sent: Thursday, June 13, 2013 3:07 PM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: A Question about Target Impedance Threshold
> computation
>
> Steven, target impedance applies at the point of use. In some cases,
> interconnect impedance can become significant even at supra-audio frequencies
> in the 100's of kHz, but almost always is an issue by the low Mhz. The
> target Z relation is also just a guideline. It assumes resistive Z which is
> rarely the case over the frequency range any given PDN needs to support.
>
> Steve.
> On 6/13/2013 1:32 PM, Steven J Ohlsen wrote:
>> Hello,
>> I am somewhat new to the world of Power Integrity. I hope this isn't
>> a dumb question, but I can not find any answer in the books I have or
>> online either. I understand that the equation for Target Impedance
>> is (allowed Voltage Variation)/(max change of current). However this
>> seems like a
>> "50,000 ft" rule-of-thumb. If your design meets this criteria then
>> all is well. But if your design has difficulty reaching this
>> impedance target then what. My observation is that when you get down
>> to the board level for example, there can be 30-40 balls on the
>> voltage regulator (and maybe multiple voltage regulators), and 50-100
>> balls on the device under test, and numerous decoupling capacitors
>> scattered around, between what points does the target impedance apply?
>> If you look at the board geometries then the current from Voltage
>> Regulator to Device may travel through a 1-inch (or more) wide path
>> on the power plane. Current is also provided by the decoupling
>> capacitors whose current (probably) has a different path to the
>> device under test . It seems that the current portion of the target
>> impedance equation varies from point to point on the board depending
>> on a host of very complicated relationships. Simply dividing the
>> current portion of the target impedance equation by the number of
>> balls on the voltage regulator or by the number of balls on the
>> device under test also seems incorrect. Is there a more design specific
>> method to compute the target impedance?
>>
>> Thank You all for your responses.
>> Steven Ohlsen
>>
>>
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>>
>
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Steve Weir
IPBLOX, LLC
1580 Grand Point Way
MS 34689
Reno, NV 89523-9998
www.ipblox.com
(775) 299-4236 Business
(866) 675-4630 Toll-free
(707) 780-1951 Fax
All contents Copyright (c)2013 IPBLOX, LLC. All Rights Reserved.
This e-mail may contain confidential material.
If you are not the intended recipient, please destroy all records and notify
the sender.
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