[SI-LIST] Re: A Question about Target Impedance Threshold computation

  • From: steve weir <weirsi@xxxxxxxxxx>
  • To: "Smith, Larry" <larrys@xxxxxxxxxxxxxxxx>
  • Date: Sun, 30 Jun 2013 22:32:22 -0700

On 6/30/2013 9:50 PM, Smith, Larry wrote:
> Hi all, just catching up on some back email here..  The target impedance 
> concept can be applied at many levels of assembly.

> Lots of good comment snipped

> In summary, it is highly probable that all circuits on the PCB will draw DC 
> current at the same time and the VRM must be sized accordingly.  But as we 
> get up into the 1 MHz, 10 MHz, 100 MHz and 1 GHz bands, the probability of 
> drawing transient currents in phase at the same frequency greatly diminishes. 
>  The target impedance at the different chip locations on the PCB should 
> reflect this in different frequency bands.
>
> Regards,
> Larry Smith
Not only all those good comments, but as frequency goes up peak currents 
become spatially isolated.  That's both a good and a bad thing.

Steve
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On 
> Behalf Of steve weir
> Sent: Thursday, June 13, 2013 3:07 PM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: A Question about Target Impedance Threshold computation
>
> Steven, target impedance applies at the point of use.  In some cases, 
> interconnect impedance can become significant even at supra-audio frequencies 
> in the 100's of kHz, but almost always is an issue by the low Mhz.  The 
> target Z relation is also just a guideline.  It assumes resistive Z which is 
> rarely the case over the frequency range any given PDN needs to support.
>
> Steve.
> On 6/13/2013 1:32 PM, Steven J Ohlsen wrote:
>> Hello,
>> I am somewhat new to the world of Power Integrity.  I hope this isn't
>> a dumb question, but I can not find any answer in the books I have or
>> online either.  I understand that the equation for Target Impedance is
>> (allowed Voltage Variation)/(max change of current).  However this
>> seems like a
>> "50,000 ft" rule-of-thumb.  If your design meets this criteria then
>> all is well.  But if your design has difficulty reaching this
>> impedance target then what.  My observation is that when you get down
>> to the board level for example, there can be 30-40 balls on the
>> voltage regulator (and maybe multiple voltage regulators), and 50-100
>> balls on the device under test, and numerous decoupling capacitors
>> scattered around, between what points does the target impedance apply?
>> If you look at the board geometries then the current from Voltage
>> Regulator to Device may travel through a 1-inch (or more) wide path on
>> the power plane.  Current is also provided by the decoupling
>> capacitors whose current (probably) has a different path to the device
>> under test .  It seems that the current portion of the target
>> impedance equation varies from point to point on the board depending
>> on a host of very complicated relationships.  Simply dividing the
>> current portion of the target impedance equation by the number of
>> balls on the voltage regulator or by the number of balls on the device
>> under test also seems incorrect.  Is there a more design specific method to 
>> compute the target impedance?
>>
>> Thank You all for your responses.
>> Steven Ohlsen
>>
>>
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>
> --
> Steve Weir
> IPBLOX, LLC
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-- 
Steve Weir
IPBLOX, LLC
1580 Grand Point Way
MS 34689
Reno, NV  89523-9998
www.ipblox.com

(775) 299-4236 Business
(866) 675-4630 Toll-free
(707) 780-1951 Fax

All contents Copyright (c)2013 IPBLOX, LLC.  All Rights Reserved.
This e-mail may contain confidential material.
If you are not the intended recipient, please destroy all records
and notify the sender.

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