[SI-LIST] A Question about Target Impedance Threshold computation

  • From: Steven J Ohlsen <sjohlsen@xxxxxxxxxxxx>
  • To: si-list@xxxxxxxxxxxxx
  • Date: Thu, 13 Jun 2013 13:32:15 -0700

Hello,
I am somewhat new to the world of Power Integrity.  I hope this isn't a 
dumb question, but I can not find any answer in the books I have or online 
either.  I understand that the equation for Target Impedance is (allowed 
Voltage Variation)/(max change of current).  However this seems like a 
"50,000 ft" rule-of-thumb.  If your design meets this criteria then all is 
well.  But if your design has difficulty reaching this impedance target 
then what.  My observation is that when you get down to the board level 
for example, there can be 30-40 balls on the voltage regulator (and maybe 
multiple voltage regulators), and 50-100 balls on the device under test, 
and numerous decoupling capacitors scattered around, between what points 
does the target impedance apply?  If you look at the board geometries then 
the current from Voltage Regulator to Device may travel through a 1-inch 
(or more) wide path on the power plane.  Current is also provided by the 
decoupling capacitors whose current (probably) has a different path to the 
device under test .  It seems that the current portion of the target 
impedance equation varies from point to point on the board depending on a 
host of very complicated relationships.  Simply dividing the current 
portion of the target impedance equation by the number of balls on the 
voltage regulator or by the number of balls on the device under test also 
seems incorrect.  Is there a more design specific method to compute the 
target impedance?

Thank You all for your responses.
Steven Ohlsen


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