[SI-LIST] Re: 8 bit async. parallel bus on back plane

  • From: asparkman@xxxxxxxxxxxxx
  • To: steve.xlin@xxxxxxxxx
  • Date: Fri, 16 Jun 2006 23:25:48 -0500

Steve L,
You didn't say what the "toggle" rate is or how long the stubs on the daughter 
cards are.  Are all 
of the receivers level 
senstive or are some of them edge sensitive?

Aubrey


----- Original Message -----
From: steve weir <weirsi@xxxxxxxxxx>
Date: Friday, June 16, 2006 4:05 pm
Subject: [SI-LIST] Re: 8 bit async. parallel bus on back plane
To: steve.xlin@xxxxxxxxx, si-list@xxxxxxxxxxxxx

> Steve, transmission line continuity is the most important issue, 
> particularly on the timing strobe(s).  It is not how far you go, 
> but 
> how much you disrupt the continuity relative to the bandwidth you 
> enclose with both the signal rate and rise/fall times.
> 
> Steve.
> At 11:13 AM 6/16/2006, Steve Lin wrote:
> >Dear friends,
> >
> >
> >I have a simple design and see if you guys can give me some advices.
> >
> >
> >
> >I am planning to run a parallel bus (8 data bit, few address 
> lines, /CS,
> >/OE, /WE, etc) on the back plane.  The bus will go thru 6 loads in 
> a daisy
> >chain fashion (6 back plane connectors), and is asynchronous that 
> can have
> >read/write access time of few hundreds nano-seconds (access timing is
> >programmable and can be quite relaxed).  The total length of the 
> bus would
> >approximately be around 50" (including the traces on daughter cards).
> >
> >
> >
> >The driving buffer I am using is SN74ALVTH16244 which is a 32mA 
> driver.>
> >
> >
> >Do I need some sort of termination on the bus to avoid ringing?
> >
> >What are the most important things that I should keep an eye on?
> >
> >
> >
> >Thanks
> >
> >
> >
> >Steve
> >
> >
> >
> >
> >
> >
> >
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