[SI-LIST] Re: 8 bit async. parallel bus on back plane
- From: "Lee Ritchey" <leeritchey@xxxxxxxxxxxxx>
- To: "Steve Lin" <steve.xlin@xxxxxxxxx>, si-list@xxxxxxxxxxxxx
- Date: Fri, 16 Jun 2006 14:02:29 -0700
Steve,
It would be best if you simulated the proposed net topology to see how it
will behave. Good chance it won't work properly.
> [Original Message]
> From: Steve Lin <steve.xlin@xxxxxxxxx>
> To: <si-list@xxxxxxxxxxxxx>
> Date: 6/16/2006 11:24:56 AM
> Subject: [SI-LIST] 8 bit async. parallel bus on back plane
>
> Dear friends,
>
>
> I have a simple design and see if you guys can give me some advices.
>
>
>
> I am planning to run a parallel bus (8 data bit, few address lines, /CS,
> /OE, /WE, etc) on the back plane. The bus will go thru 6 loads in a daisy
> chain fashion (6 back plane connectors), and is asynchronous that can have
> read/write access time of few hundreds nano-seconds (access timing is
> programmable and can be quite relaxed). The total length of the bus would
> approximately be around 50" (including the traces on daughter cards).
>
>
>
> The driving buffer I am using is SN74ALVTH16244 which is a 32mA driver.
>
>
>
> Do I need some sort of termination on the bus to avoid ringing?
>
> What are the most important things that I should keep an eye on?
>
>
>
> Thanks
>
>
>
> Steve
>
>
>
>
>
>
>
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