[SI-LIST] 8 bit async. parallel bus on back plane

  • From: "Steve Lin" <steve.xlin@xxxxxxxxx>
  • To: <si-list@xxxxxxxxxxxxx>
  • Date: Fri, 16 Jun 2006 11:13:09 -0700

Dear friends,
 

I have a simple design and see if you guys can give me some advices. 

 

I am planning to run a parallel bus (8 data bit, few address lines, /CS,
/OE, /WE, etc) on the back plane.  The bus will go thru 6 loads in a daisy
chain fashion (6 back plane connectors), and is asynchronous that can have
read/write access time of few hundreds nano-seconds (access timing is
programmable and can be quite relaxed).  The total length of the bus would
approximately be around 50" (including the traces on daughter cards). 

 

The driving buffer I am using is SN74ALVTH16244 which is a 32mA driver.

 

Do I need some sort of termination on the bus to avoid ringing?  

What are the most important things that I should keep an eye on?

 

Thanks

 

Steve

 

 



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