[SI-LIST] Re: 6 layers stackup
- From: Scott McMorrow <scott@xxxxxxxxxxxxx>
- To: Todd Hubing <HUBING@xxxxxxxxxxxxxxxxxxxx>
- Date: Wed, 27 Feb 2008 11:59:13 -0500
Todd Hubing wrote:
> The inductance associated with the internal construction of the
> capacitor is only going to be a relevant factor when the capacitor is
> mounted on (or embedded in) the planes.
This is only partially true. Total inductance measured for a mounted
capacitor is:
Lmount = Lcap + Lvia + Lspread + Lport
where I define
Lcap = inductance of the capacitor and mounting structure (capacitor
body, plates, pads, vias) above the 1st plane.
Lvia = inductance of the coupled via stack between internal plane cavities
Lspread = spreading inductance through the plane
Lport = inductance of the measurement port(s) down to the power/ground
planes
We can stipulate that for all measurements Lport is identical, and that
for capacitor mounting structures of approximately the same spatial
extent, Lspread is identical. We can also stipulate that if any of
these inductances is much much larger than any other, that particular
inductance will dominate. Thus, it is imperative that we have a method
within our fixture for de-embedding Lport + Lspread, so that we can make
a determination of whether we are truly measuring the board or the
capacitors. If it turns out that Lport + Lspread >> Lvia + Lcap, then
even a zero inductance mounted capacitor will have no impact on measured
PDS performance. When this is the case, good capacitors can not help a
bad board.
Once we have characterized the fixture and determined that it is
reasonably capable of measuring what we want to measure, then we can use
further de-embedding to divide the problem into it's parts. We can
define a fixture to measure Lport + Lspread + Lvia. Along with our
previous Lport + Lspread measurement, we can determine Lvia. Then with
full device measurement (Lport + Lspread + Lvia + Lcap) we can determine
the capacitor inductance.
Steve has designed such a fixture that I have correlated to multiple 3D
full-wave solvers and methods, including CST MWS TD, CST MWS FD, Ansoft
SIwave, for 0402 capacitors . The fixture has a PRF/SRF ratio of better
than 50:1, making it highly accurate for the measurement of capacitors
and capacitor via mounting structures. I presented a paper on this at
DesignCon, slides from which are available on our website:
http://www.teraspeed.com/papers/DC08_FullWaveCapacitorModeling_paper.pdf
http://www.teraspeed.com/papers/DC08_FullWaveCapacitorModeling_pres.pdf
Once we have calibrated our fixtures and our field solver, it is now
possible to investigate various capacitor types and mounting structures,
whether they be 2 terminal, 4 terminal, 8 terminal ... etc. And we can
normalize our results in order to develop figures of merit.
Todd Hubing wrote:
> The inductance associated with the internal construction of the
> capacitor is only going to be a relevant factor when the capacitor is
> mounted on (or embedded in) the planes.
Here are some of our specific measurements:
3 mil plane separation
3 mil distance from capacitor to upper plane
X2Y - 118 pH
0402 4-via - 378 pH
0402 2-via - 452 pH
3 mil plane separation
12 mil distance from capacitor to upper plane
X2Y - 154 pH
0402 4-via - 450 pH
0402 2-via - 626 pH
In the case of John Zasio's article on the Speeding Edge:
http://www.speedingedge.com/PDF-Files/X2Y%20vs%200402%20081605.pdf
Measurements on 3 mil plane separation on the V1 plane about 15 mils
down in the stack and 3 mils dielectric thickness
X2Y - 350 pH
0402 4-via 1mm space - 480 pH
Clearly we have reasonable correlation between our 0402 measurements and
Speeding Edge measurements.
Speeding Edge - 480 pH @ 15 mils down
Teraspeed - 450 pH @ 12 mils down
However, when we compare the X2Y results we have:
Speeding Edge - 350 pH
Teraspeed - 154 pH
Clearly we have a large discrepancy. An analysis of the PCB layout, as
Steve has done, shows that the difference is attributable to the
extremely poor layout used by John on the X2Y parts. It is my opinion
that the conclusions made by John Zasio in the Speeding Edge paper is
attributable to this poor layout for the X2Y capacitor, vs. a highly
optimized layout for the 0402 capacitor. Once the layout is corrected,
we would expect to see results that correlate with our own measurements,
which would show the following inductances at 15 mil depth
X2Y - 158 pH
0402 - 480 pH
X2Y to 0402 inductance ratio of 1:3.1, which would match our own
measurements and show a 3.1:1 performance improvement. Based on this,
we can easily say the following for that particular configuration:
Properly mounted X2Y devices utilize 33% few parts to achieve the same
inductance as 0402 capacitors with 4-vias
Properly mounted X2Y devices utilize 50% less vias to achieve the same
inductance as 0402 capacitors with 4-vias
It is not "just" the internal inductance of this capacitor that is
superior. The via array pattern that the X2Y capacitor facilitates is
far superior to the best that can be done with an 0402 2-terminal
device. This is a result of the terminal and plate structure of the
device. Inductance advantages extend down the vias into the PCB.
Todd, I hope that you reconsider your previous posting and provide some
supporting evidence to all of your statements, including the following:
Todd Hubing wrote:
> Nevertheless, two-terminal caps can be mounted much more effectively
> than they are in the papers that show X2Y caps performing 2 to 3 times
> better.
>
>
As a consultant who designs power distribution systems for many
customers each year, if there is a better two-terminal capacitor
mousetrap, I would love to see it. Thus far I've not seen anything
published in the literature, or commercial claims that can be confirmed
through measurement, analytics, or computational electromagnetics. If
you have references I am not aware of, I would be quite interested. I
suspect that other subscribers to the Silist would also be interested.
Best regards
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