[SI-LIST] Re: 6 Layer microvia stackup
- From: "Dhiraj Kiran" <Dhiraj.Kiran@xxxxxxxxxxx>
- To: <andrew.seddon@xxxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Wed, 11 Jan 2006 07:47:53 -0500
Hello Andrew,
I really doudt if this stack-up is doable...
Maybe u can manage a 50um(2mils) prepeg, but I doubt if the PCB
manufacturers would support a core of thickness 50um (2mils).
Assuming that you take care of the thickness issue, I am not really sure
that you would be able to achieve good=20
impedance control for your traces in SIG1 & SIG3 layers. The reason for
this being that your GND would be more or less
continuous in Layer-4, but I doubt if you will be able to do the same on
the top layer. If you still want to continue with=20
this stackup, you can ensure impedance control by routing signals on
SIG1 & SIG2 such that the GND on the TOP layer=20
encapsulates these traces without any break in between.
It is highly necessary for you to maintain orthogonality on your signal
layers as there is a very nice capacitive coupling
between them.
Best Regards,
Dhiraj=20
=20
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Andrew Seddon
Sent: Wednesday, January 11, 2006 5:54 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] 6 Layer microvia stackup
Hello,
I'm currently designing a really dense PCB and was wondering if anybody
has comments with regards to the signal integrity of the following
stack;=20
1 GND =09
50um ER1 3.6
2 SIG 1 75um trace for 50 ohm
50um ER1
3 SIG 2 100um trace for 50 ohm
100um ER2 4.2
4 GND
50um ER1 3.6
5 PWR
50um ER1 3.6
6 MISC
Basically the plan is to do all routing on layers 2 and 3. The top layer
is mostly BGA's and floods to a pretty solid GND plane. All lands on
layers 1 and 6 are micro via in pad. So microvias from layers; 1-2, 2-3
. These can be stacked to create a 1-3 via.
So I have a few worries about this stack;
1. Can't route SIG1+SIG2 orthogonally. The impedance calculations are
based on each layer being calculated as an independent offset stripline.
Is this valid and will there be a lot of cross talk on traces running
underneath each other.
2. Getting controlled impedance on tracks that switch between 2 and 3
could be tricky.
Lastly I was wondering if anybody knows a good reference for micro via
stack's. It seems that you basically have to throw away the stacks used
for conventional via's. For example if you have 3 micro via layers on
each side
(3+n+3) where do your planes go?
Best regards,
Andrew
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=20
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