[SI-LIST] Re: 6 Layer Stack-up (TANSTAAFL)

  • From: "Scott McMorrow" <scott@xxxxxxxxxxxxx>
  • To: john.matthews@xxxxxxxxxxxxxxxxx
  • Date: Tue, 16 Sep 2003 03:19:32 -0700

John,
TANSTAAFL (There ain't no such thing as a free lunch.)

As an engineer, we all get a chance to trade off cost vs. performance, 
or one type of performance vs. another.  If you insist on using a 
6-layer stackup, then you have to deal in tradeoffs. 

Generally, I have found that to obtain good performance in EMI and SI 
there needs to be a balance in the number of power/ground planes vs. the 
number of signal planes.  When the number of signal planes is greater 
than the number of power/ground planes there is a compromise in 
performance somewhere.  A 6-layer board is just one of those compromises.

Chris is right.  (He usually is.)  A stackup that has S-P-S-S-G-S 
(stackup 1)  is usually a better compromise for both SI and EMI than a 
S-S-P-G-S-S (stackup 2).  Stackup 2, except for really, really, really, 
really slow signals, is just awful.  Any trace routed on the outer 
layers has abysmal impedance control. For a 0.063" board, the EMI loop 
area is huge between the packages and breakout traces and the image 
plane.  I guess if a designer forgot to use decoupling capacitors, or 
didn't follow modern capacitor mounting rules (see the many numerous 
papers by Larry Smith, Ray Anderson, and Istvan Novak of Sun), then 
stackup 2 might be better, but you really have to try hard.

In my days, I have designed quite a few 6-layer server motherboards that 
performed exceptionally well in both the signal integrity and EMI 
areas.  I have always used stackup 1.  If you'd like to improve the EMI 
performance of the stripline layers (which is already quite good) then 
utilize Chris' suggestion of a ground via faraday cage around the edge 
of the board.  You'll even get extra points if you randomly vary the 
spacing to guarantee non-uniform aperture width around the edge.

If I had my way, I'd always design with a balanced number of signal and 
power/ground planes.  The following 8-layer stackup will always perform 
better than either of the 6-layer stackups

S-P-G-S-S-P-G-S

In general, I'd recommend designs which use paired power/ground planes 
and stripline routing layers.  Routing of major high speed signals on 
microstrip layers can be problematic.  Removing the power/ground planes 
from the vicinity of the package mounting layers, as is done in stackup 
2 is an EMI and SI accident waiting to happen.  I'm not saying that this 
sort of stackup and routing can't be made to work well, it's just that 
in unskilled hands that is not likely.


regards,

scott

-- 
Scott McMorrow
Electromagnetic Field Wrangler
Teraspeed Consulting Group LLC
2926 SE Yamhill St.
Portland, OR 97214
(503) 239-5536
http://www.teraspeed.com



John Matthews wrote:

>Chris
>
>Definitely worth thinking about, I think that the reason I didn't go that
>way in
>the first place was that I thought I would have better decoupling if power
>and
>ground were adjacent.
>
>Of course I neglected the fact that top and bottom would not have reference
>planes,
>which was partly corrected second time round with the copper fills.
>
>There seems to be a bit of compromise involved. We fix one problem at the
>expense of
>another.
>
>John
>
>
>
>
>-----Original Message-----
>From: si-list-bounce@xxxxxxxxxxxxx
>[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Chris Cheng
>Sent: 15 September 2003 21:33
>Cc: si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] Re: 6 Layer Stack-up
>
>
>John,
>Why not S-P-S-S-G-S and bury all your fast signals inside ?
>
>-----Original Message-----
>From: john.matthews@xxxxxxxxxxxxxxxxx
>[mailto:john.matthews@xxxxxxxxxxxxxxxxx]
>Sent: Saturday, September 13, 2003 3:57 PM
>To: chris.cheng@xxxxxxxxxxxx
>Cc: si-list@xxxxxxxxxxxxx
>Subject: Re: [SI-LIST] Re: 6 Layer Stack-up
>
>
>We recently completed a board, having had a lot of trouble with EMI.
>
>We started with S-S-P-G-S-S (layers 1-2-3-4-5-6) and found that our
>emissions (radiated) were such that we didn't have a hope in hell of
>passing Class B.
>
>We then modified the board components single sided) in the following way:
>
>1.. We identified the slowest and fastest signals.
>2.. Fastest signals went on layers 2 and 5, preferably layer 5.
>3.. Slowest signals went on layers 1 and 6.
>4.. On layer 6, we took extreme care to lay out the slow signals,
>    such that we could copper fill afterward and then stitch around the
>    edge of the board to the ground plane. We took care of the slow
>    signals so that they didn't cut the copper fill too much, i.e.
>    localised them and kept them in one dimension.
>5.. We did something similar with Side 1, althouth this isn't as effective
>    since we've too much discontinuity with component bodies.
>
>The result was that we can pass emissions testing now. However it meant we
>had to hand route the board (lots of work).
>
>I'm trying to learn lessons from this to carry into future designs. The
>flooding definitely helped. We did it beacuse we knew that we would pass
>test if we put our board on a metal box, rather than plastic, so we though
>why not try to get some of the Farady effect on the PCB itself.
>
>I agree with the point that the noise is still there .. you can't get rid
>of harmonics as you need them for SI, so they'll come out somewhere. In
>our case, it looks as of our cables are a bit nosier ..
>
>I'm interested in comments. we had loads of decoupling, but even using
>10pF decouplers could not get rid of the higher harmonics.
>
>John
>
>
>
>  
>
>>In reality people stitch ground vias along the edge of the PCB to form a
>>faraday cage to confine the stripline radiation within the PCB.
>>-----Original Message-----
>>From: Ravinder.Ajmani@xxxxxxxx [mailto:Ravinder.Ajmani@xxxxxxxx]
>>Sent: Friday, September 12, 2003 7:22 PM
>>To: chris.cheng@xxxxxxxxxxxx
>>Cc: si-list@xxxxxxxxxxxxx
>>Subject: Re: [SI-LIST] Re: 6 Layer Stack-up
>>
>>
>>
>>Yes, that is what I also get when I do EMI simulation with MoM simulator.
>>However in actual practice, you can't control EMI by simply burying it
>>between planes.  The energy will always find a way to come out and
>>radiate.
>>
>>Regards, Ravinder
>>Server PCB and Flex Development
>>Hitachi Global Storage Technologies
>>
>>Email: Ravinder.Ajmani@xxxxxxxx
>>
>>
>>
>>
>>
>>      Chris Cheng <chris.cheng@xxxxxxxxxxxx>
>>Sent by: si-list-bounce@xxxxxxxxxxxxx
>>
>>
>>09/12/2003 01:50 PM
>>Please respond to chris.cheng
>>
>>
>>
>>        To:
>>        cc:        si-list@xxxxxxxxxxxxx
>>        From:        si-list-bounce@xxxxxxxxxxxxx
>>        Subject:        [SI-LIST] Re: 6 Layer Stack-up
>>
>>
>>
>>
>>
>>Not necessary true.
>>The key is what signals do you put on the microstrip layer that is
>>reference
>>to P-plane. If you are stupid enough to put highspeed signals that has
>>nothing to do with P-power on it, they will need a return path and will
>>most
>>likely exhibit itself as ground/power bounce on signals and high EMI
>>radiation. In that case S-S-P-G-S-S provides the lower impedance return
>>path
>>through the plane capacitance. But that's not as good as if you bury the
>>highspeed signals as striplines inside the S-P-S-S-G-S stackup. I can
>>easily
>>show you example of bad EMI when I force highspeed signals on the
>>outer-layer referencing a power plane that has nothing to do with I/O
>>power
>>and how it can be "improved" with a thin core P-G added. But I can also
>>shows you if I bury them as stripline, the EMI will be even better than
>>with
>>thin core.
>>
>>    
>>
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