[SI-LIST] Re: 50 Ohm Via?
- From: "Loyer, Jeff" <jeff.loyer@xxxxxxxxx>
- To: <joel@xxxxxxxxxx>
- Date: Sat, 12 Jan 2008 09:53:43 -0800
Some thoughts, in no particular order (and targeted for High Volume
Manufacturing products).
* A paper you might find pertinent is "System Level Impact of
Stitching Vias and Capacitors for High-Speed Differential Links",
available as:
Electronic Components and Technology Conference, 2007. ECTC '07.
Proceedings. 57th
Publication Date: May 29 2007-June 1 2007
On page(s): 357-36
ISSN: 0569-5503
ISBN: 1-4244-0985-3
* Keep in mind how stackup-specific any controlled impedance via
design will be. A via that appears >50 ohms in a thick, lower-layer
count board (say 100 mils, 6 layers), might well appear capacitive (< 50
ohms) when the number of layers is increased. Plug-in cards (or desktop
boards) are often 60 mils thick, and only have 4 layers. For a server
design, you'd need different via designs for your baseboard versus
risers and/or plug-in cards.
* Any realistic, precise via design would have to account for
manufacturing variation, giving a "family" of possible impedances,
rather than a single one. The impedance variations might be too small
to matter, but should be understood. For differential vias, for
instance, drill accuracy might play a significant role in the impedance.
* Of course, each controlled-impedance via is only valid for a
particular layer entry/exit scheme.
* These make controlled-impedance vias very challenging for
actual products.
* Add to these points the real-estate a controlled-impedance via
might require (especially if you start talking about surrounding each
signal via with multiple ground vias), and I end up being very skeptical
that they are suitable for anything other than research or
low-volume/high-performance/long-leadtime/high-price products. For
designs where cost and TTM (Time-To-Market) are primary drivers, ugly
vias will continue to be necessary evils in our design. Some things
that can be done to minimize their impact (and I invite others to add to
the list):
o Floorplan your high speed busses first, to optimize their
topology for layer transitions:
* Minimize the number of transitions (vias) from driver to
receiver, including connectors and risers. Let your kHz or low MHz
signals jump around from layer to layer, while your GHz signals continue
on their dedicated layers.
* When transitioning, go all the way through the board,
minimizing the stub. For multi-board designs, this can be very
challenging, but those are probably where this will be the greatest
issue, also.
o Provide adequate ground stitching vias near transitions.
I think applying guidelines like these, and absorbing the "hit" from the
vias that are necessary, will be more realistic than complex, 3-D via
design for most products.
I'd also add my 2 cents about loosely versus tightly coupled... As you
point out, neither is without shortcomings. I do believe, however,
you'll want the two halves of a differential pair to be in close
proximity at any transitions - they'll be more "tolerant" of the
impedance discontinuity (and any other impedance discontinuities). I
would agree with your comment regarding wider trace widths being an
advantage to looser coupling, but am not aware of any degradation of
risetime from tight coupling, except perhaps if the traces are narrower.
Disclaimer:
The content of this message is my personal opinion only and although I
am an employee of Intel, the statements I make here in no way represent
Intel's position on the issue, nor am I authorized to speak on behalf of
Intel on this matter.
Jeff Loyer
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Joel Brown
Sent: Wednesday, January 09, 2008 8:30 PM
To: wolfgang.maichen@xxxxxxxxxxxx; luant@xxxxxxxxxxx
Cc: si-list@xxxxxxxxxxxxx; si-list-bounce@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: 50 Ohm Via?
Wolfgang,
Your point about how much simulation is worthwhile is well taken.
I work for a small company and wear a lot of hats, I am not a full time
SI
engineer. We do have some tools such as Hyperlynx and Hspice which in my
opinion have been under utilized. I know Hyperlynx claims to have some
GHz
via modeling capability but I am not sure how accurate it is and I don't
think it takes the return path such as stitching vias into account. I
have
been trying to do more simulation as time allows and learning along the
way.
It's certainly not easy to learn multiple simulation environments and
all
the pitfalls. I have yet to get to the point to where I can correlate
measurements against simulations.
How would I know what the prop delay through a via will be?
To Chris:
I have been reading several places that recommend using loosely coupled
differential pairs, that is why I mentioned 50 ohms. I know there are
religious beliefs about tightly coupled vs loosely coupled pairs. The
material I read regarding loosely coupled pairs mentioned advantages
such as
wider trace widths for a given impedance and avoiding degradation of
rise
time caused by coupling between signals within a pair.
Thanks - Joel
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On
Behalf Of wolfgang.maichen@xxxxxxxxxxxx
Sent: Wednesday, January 09, 2008 7:19 PM
To: luant@xxxxxxxxxxx
Cc: si-list@xxxxxxxxxxxxx; si-list-bounce@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: 50 Ohm Via?
As a simple rule of thumb:
Usually not very important if the prop delay through the via is less
than
about 1/6th of your signal rise time (you may be able to get away with
1/4th). Rise time is much more important than bit rate or clock
frequency.
As to the number of vias - this can of course aggravate the problem; but
on the other hand, I wouldn't attempt to design a 10 Gb/s channel and
put
in more than maybe two vias...
just my 2 cents
Wolfgang
"Tony Luan" <luant@xxxxxxxxxxx>
Sent by: si-list-bounce@xxxxxxxxxxxxx
01/09/2008 07:06 PM
Please respond to
luant@xxxxxxxxxxx
To
<si-list@xxxxxxxxxxxxx>
cc
Subject
[SI-LIST] Re: 50 Ohm Via?
How critical the characteristic impedance of via transition is? It
depends on the bit rate, channel insertion loss and the number of vias
on each channel.=20
BR
Tony
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Harry Selfridge
Sent: Wednesday, January 09, 2008 6:50 PM
To: 'SI LIST'
Subject: [SI-LIST] Re: 50 Ohm Via?
There was an article written about controlled impedance vias several=20
years ago by Thomas Neu of Texas Instruments. I haven't seen any=20
followup articles by anyone on the subject since. You can read Neu's=20
article online at:
http://www.edn.com/index.asp?layout=3Darticle&articleid=3DCA324403 .
Others may have experienced different results, but I've never found=20
controlled impedance vias to be necessary or useful. The distances=20
involved in a via are so short that any pretense of matching=20
impedance is negligible compared with other variations that you might=20
encounter over the full length of a signal path. One board we built=20
for a customer provided two signal paths, one with Neu's controlled=20
impedance vias, and duplicates without. Testing of the loaded board=20
showed no appreciable difference in performance, and the loss of=20
board space to the structure necessary to achieve the controlled=20
impedance vias was considerable.
Regards - Harry
At 05:51 PM 1/9/2008, you wrote:
>Is there such a thing as a design methodology for designing a PCB via
with
>50 ohm impedance, or does it have to be done iteratively using a 3D
field
>solver?
>Are controlled impedance vias necessary, worthwhile or helpful for
>multi-gigabit serial links running at 1 to 5 Gbps?
>
>
>
>Thanks - Joel
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