[SI-LIST] 4 month Signal Integrity Contract at Intel in Santa Clara, CA

  • From: "James Van" <Jvan@xxxxxxxxxxxxxx>
  • To: <si-list@xxxxxxxxxxxxx>
  • Date: Thu, 10 Aug 2006 17:54:55 -0700

Hi All,
I have a 4 month signal integrity contract with Intel in Santa Clara.
I'm attaching a copy of the job description. Please contact me at
jvan@xxxxxxxxxxxxxx if interested. 
Signal integrity engineer
. Responsible for system-level (utilizing Intel Xeon and server chip
sets) SI test, validation, debug, measurement & correlation, which
include FSB, FBD, PCI-Express Gen1/Gen2, Clocks, and misc. signals.
. Assist board design engineers to power on, bring up, debug, and
validate the new design, taking responsibility for the design robustness
over temperature, voltage, and frequency.
. Set up and debug the SI simulation tool environment.
5 years.
. Hands-on experience of use of high-speed signal integrity lab
equipment, e.g. high-bandwidth scopes, TDR, Logic Analyzer, etc.
. Hands-on experience of debug of high-speed signal integrity issues, in
GHz differential signals & clocks
. Understand all basic SI fundamentals, such as lossy transmission
lines, crosstalk, S-parameter etc.
. Know fundamentals about board design, impact of stackup, trace
geometries, etc.
. Good understanding of the power distribution network and its impact on
. HSPICE experience is a must, need be able to create a Spice deck from
scratch if necessary.
. Know to how work with IBIS and Hspice behavior/transistor models.
. Familiarity with high-speed serial link bus terminology and SI
simulation methodology.
. Experience in SI measurement and correlation
. Be a self-starter and good team player.
. Nice to have skills include
. Knowledge of PCI Express SI design methodology
. Familiar with PCI Express signal quality requirements
. Know how to modify/create Perl scripts to automate the design process 
James Van-Recruiter
Trinite Inc.
Office: (650) 210-2010//(888) 872-3526
Mobile: (650) 823-2125
f (650) 210-8989

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