[SI-LIST] Re: 4 layer board stack up
- From: Ritchey Lee <leeritchey@xxxxxxxxxxxxx>
- To: doug@xxxxxxxxxx
- Date: Mon, 15 Oct 2001 09:16:17 -0700
Doug is right. However, when one locates the power planes close enough to the
surface to create good environments for the traces, the plane capacitor is
nearly nonexistent. This is a regular problem with four layer PC mother
boards.
We solve that problem in one of two ways.
1. Use a four layer BGA package with a plane capacitor built into it. (The
Inetl Celeron chips do this.)
2. Fill in the unused space on the signal layers with copper and connect it
to the appropriate power rail to add additional plane capacitance. ( We do
this routinely with the PCMCIA form factor PCBs.)
Lee
Doug Brooks wrote:
> It seems to me there are two guidelines that, if both met, define a good
> board stack-up:
> 1. Every trace must be immediately adjacent to a reference plane.
> 2. There must be at least one power-ground (capacitive) plane pair.
>
> Your first example meets both these guidelines but the second one doesn't.
> Therefore, the first one is better.
>
> Doug Brooks
>
> At 02:19 PM 10/10/2001 +0800, you wrote:
>
> >Hi all,
> >
> >Which is a better 4 layer stack up configuration?
> >
> >Signal 1
> >Ground
> >Power
> >Signal 2
> >
> >OR
> >
> >Signal 1
> >Ground
> >Signal 2
> >Power
> >
> >It seems like the 2nd option gives us more flux cancellation as a Ground
> >plane is sandwiched between Signal 1 and Signal 2.
> >
> >Any comments??
> >
> >
> >Thanks!
> >
> >
> >Erwin Seow
>
> ***********************************************************
> Doug Brooks' book, "Electrical Engineering for the Non-Degreed Engineer is
> now in its 3rd printing. Learn about it at www.ultracad.com
>
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