[SI-LIST] Re: 24-layer PCB Stack-up
- From: pjabbaz@xxxxxxxxxxx
- To: t.l.jackson@xxxxxxxx
- Date: Fri, 12 Mar 2004 18:39:48 +0000
See suggested 24 layer stackup below
It will yield true 8 signal routing layers plus Top and Bottom
7 GND PLANES
5 PWR PLANES TWO DEDICATED FOR POWER SPLITS SUCH AS LOCAL CORE POWERS , VTT ETC
There not much need to isolate each signal layer with a plane in between as
long as you keep the following in mind,
The spacing between adjacent signal to signal layers is greater than the
spacing of signal to reference plane, also keep the routing at 90 degress from
each other.
24 layer-stackup
L1- TOP
L2-GND
L3-SIG HOR
L4-SIG VER
L5-GND
L6-PWR
L7-SIG HOR
L9-SIG VER
L10-GND
L11-PWR SPLIT POWER HERE
L12-GND
center
L13-PWR SPLIT POWER HER
L14-GND
L15-PWR
L16-SIG VER
L18-SIG HOR
L19-PWR
L20-GND
L21-SIG VER
L22-SIG HOR
L23-GND
L24-BOTTOM
Inkra Networks
Patrick Jabbaz CID
Sr Board Layout Eng.
40971 Encyclopedia Circle
Fremont, CA 94538
Work (510) 249-4835
Mobile (408) 621-6533
patrick@xxxxxxxxx
> Chai,
>
> For the 8 signal layers that you mention, I would suggest a 22-layer
> stack-up like:
>
> 1. Signal 1
> 2. Ground
> 3. Power
> 4. Signal 2
> 5. Ground
> 6. Power
> 7. Signal 3
> 8. Ground
> 9. Power
> 10. Signal 4
> 11. Ground
> ------------------- < Insert one more Power and Ground layer pair, if
> necessary, to get to 24 layers
> 12. Power
> 13. Signal 5
> 14. Ground
> 15. Power
> 16. Signal 6
> 17. Ground
> 18. Power
> 19. Signal 7
> 20. Ground
> 21. Power
> 22. Signal 8
>
> This stack-up has 8 signal layers, 7 ground layers, and 7 power layers.
> This stack-up will produce the greatest amount of board capacitance,
> reducing the need for discrete decoupling capacitors. The inner signal
> layers are almost completely shielded, so as many traces as possible
> should be run on them, leaving a minimum amount of traces on the two
> outer signal layers. If you felt that you really needed to maximize the
> shielding, why not run a ground trace around the perimeter of the inner
> signal layers to reduce emissions or reception from the edges of the
> board?
>
> Unless this board is extremely large, I don't think 166 MHz will be a
> problem with careful layout. Tricks like putting vias on the sides of
> passive component pads, rather than outside of the pads, will do more to
> reduce parasitic inductance from decoupling than trying to minimize the
> connection lengths in the vias.
>
> That's the way I would do it based on the information you've given.
>
> TJ
> Thomas L. Jackson, P.E.
> Senior Staff System Engineer
> Department 72FS, Mechanism Products System Engineering
> Lockheed Martin Space Systems Company
> Building 149
> 1111 Lockheed Martin Way
> P.O. Box 3504
> Sunnyvale, CA 94089-3504
> Telephone: (408) 742-2013
> Facsimile: (408) 742-7701
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
> On Behalf Of Ched-Chang Chai
> Sent: Friday, March 12, 2004 1:32 AM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] 24-layer PCB Stack-up
>
>
> Dear all,
>
> I have a question about a PCB stack-up. Due to certain reasons, I must
> design a 24-layer and 5mm thick board although we will be only using 8
> signal layers. The other 16 layers will be Power or Ground. The signals
> are
> operating at 166MHz. I have a few concerns about this board:
> (1) the inductance and capacitance of through-hole via (they are 5mm
> long!).
> (2) the effect of vias to power-ground decoupling (bypass, decoupling
> capacitors).
> (3) Electromagnetic Interference.
> To minimize the above effects, I am thinking to set the stack-up as:
>
> 1. Signal
> 2. GND
> 3. Power
> 4. Gnd
> 5. Signal
> 6. Gnd
> 7. Signal
> 8. Gnd
> 9. Signal
> 10. Gnd
> 11. Signal
> 12. Gnd
> 13. Signal
> 14. Gnd
> 15. Gnd
> 16. Gnd
> .
> .
> .
> Gnd until 24 layers.
>
> I set ground and power planes at layers 2 and 3 respectively to minimize
> the
> via length associated with the bypass/decoupling capacitors. The other 5
>
> signal layers are set closest to Layer1 to minimize the via length when
> traces change layers. I sandwich the signal layer between Gnd planes to
> reduce EMI effect.
>
> Is this a good choice? How to set a stack-up that can minimize the above
>
> mentioned effects?
>
> Please advise me since I am green horn in PCB stack-up.
> Thank you very much in advance.
> --
> Regards,
> Chai
>
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