[SI-LIST] Re: 12 Layer stack
- From: steve weir <weirsi@xxxxxxxxxx>
- To: sunil bharadwaz <sunil_bharadwaz@xxxxxxxxx>
- Date: Sat, 02 Aug 2008 02:23:21 -0700
sunil, interesting assignments. The good news is that all your critical
signals are Vss referenced. The bad news is that you may have some
unpleasant PDN surprises. Pay attention to resonances in your analysis
and prototype evaluation.
Steve
sunil bharadwaz wrote:
> Hi ,
> Thanks to each & every for having replied.
>
> I want to go with the stack given below.
>
> 1)There are plenty of split planes in the design & hence i kept the power
> planes
> adjacent .
>
> 2)This is a Vertex-5 based design & Pcie has been included.
>
>
>
>
>
>
>
>
>
>
>
> 12 Layer Stack
>
>
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>
>
>
>
>
> Layer
> Stack
> Impedance
> Dielectric
> Routing
>
>
>
>
>
>
>
>
>
> 1
> Signal
> 60 ohms
>
> Components & some
> routing
>
>
>
>
>
> Thinner Dielectric
>
>
>
> 2
> Ground
> Plane
>
>
>
>
>
>
>
> Thinner Dielectric
>
>
>
> 3
> Signal
> 60 ohms
>
> Other Signals
> including SDRAM @ 133Mhz (SDR)
>
>
>
>
>
> Thicker Dielectric
>
>
>
> 4
> Signal
> 60 ohms
>
> 3.3 Volt & 1.8 Volt I/O Signals -
> Critical
>
>
>
>
>
> Thinner Dielectric
>
>
>
> 5
> Ground
> Plane
>
>
>
>
>
>
>
> Thinner Dielectric
> Burried Capacitance
>
>
> 6
> Power
> Plane
>
> 3.3 , 3.0 , 2.5 &
> 1.8 I/O Supply Voltages-Split Plane
>
>
>
>
>
> Dieclectric Thickess
> Higher
> Noise Coupling
>
>
> 7
> Power
> Plane
>
> 2.5 Volt Pcie I/O
> Supply & 2.5 , 1.25 , 1.8 Volts & may be auxillary 2.5 Volts
>
>
>
>
>
> Thinner Dielectric
> Burried Capacitance
>
>
> 8
> Ground
> Plane
>
>
>
>
>
>
>
> Thinner Dielectric
>
>
>
> 9
> Signal
> 60 ohms
>
> 2.5 Volt I/O's of
> Pcie & the Differential Pcie Signals
>
>
>
>
>
> Thicker Dielecterc
>
>
>
> 10
> Signal
> 60 ohms
>
> 3.3 Volt & 1.8
> Volt I/O Signals - Non critical
>
>
>
>
>
> Thinner Dielectric
>
>
>
> 11
> Power
> Plane
>
> 1.0
> Volt Core Supply Voltage plane & 5.0 Volt -Split Plane or may be
> auxillary 2.5 Volts
>
>
>
>
>
> Thinner Dielectric
>
>
>
> 12
> Signal
> 60 ohms
>
> Decaps & some
> routing
>
>
>
>
>
>
>
>
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>
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>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
> Total Thickness of the
> Board 1.6 mm
>
>
>
>
>
>
>
> 3)11 th layer is power (need atleast three power planes)
>
> Pls let me know.
>
> Best Regards
> Sunil.B
>
> --- On Thu, 7/31/08, Shimko, Steven R. <s.shimko@xxxxxxx> wrote:
> From: Shimko, Steven R. <s.shimko@xxxxxxx>
> Subject: [SI-LIST] Re: 12 Layer stack
> To: si-list@xxxxxxxxxxxxx
> Date: Thursday, July 31, 2008, 5:09 PM
>
> I agree Ken, that 100% orthogonality is difficult (impossible?) to
> achieve on many boards. Along with the X-Y layers, we also have routing
> guidelines that specify, for instance, given the type of signal (clock,
> stobe, data, static control line, power) how long a distance it's
> allowed to run parallel to another trace given the trace separations.
> There's a whole series of these that we give to our routing houses for
> them to follow.
>
>
> Steve
>
> -----Original Message-----
> From: Ken Cantrell [mailto:Ken.Cantrell@xxxxxxxxxxxxxxxx]
> Sent: Wednesday, July 30, 2008 5:33 PM
> To: Shimko, Steven R.; si-list@xxxxxxxxxxxxx
> Subject: RE: [SI-LIST] Re: 12 Layer stack
>
> Sunil -
> I think, as Bill says, both Prasad's stack and Bill's stack (or
> Steve's)
> will work just fine, especially at 133MHz. My only caution is that in
> very dense boards orthogonal routing is only partially achievable at
> best. If total thickness is an issue, dual stipline costs you more in
> layer height than two singles.
>
> Ken
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Shimko, Steven R.
> Sent: Tuesday, July 29, 2008 4:43 AM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: 12 Layer stack
>
>
> Our standard 12-layer stackup for a digital board (up to a couple of
> hundred Mhz) looks like
> this:
> S-P-S-S-G-S-S-P-S-S-P-G
> The signal layers adjacent to each other are always orthogonal routes (X
> on one layer, Y on the next). We generally don't do much routing, if
> any at all, on the top layer.
>
> Steve
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
> On Behalf Of Mangipudi, Prasad
> Sent: Monday, July 28, 2008 6:17 PM
> To: 'wjcsongr@xxxxxxxxxxxxxxxxxxx'
> Cc: 'SI LIST'; 'si-list-bounce@xxxxxxxxxxxxx'; 'sunil
> bharadwaz'
> Subject: [SI-LIST] Re: 12 Layer stack
>
> Bill,
> My GROUND assertion works for ALL signals, not just when passing through
> connectors.
>
> Consider a situation signals passing from one IC to another IC on a
> board. If the ICs are referenced to different voltage planes V1 and V2,
> you have to work on making the return path cross from V1 to V2. If the
> signal passes to multiple ICs, which are referenced to different
> voltage
> planes, or the signals pass through referencing other voltage planes or
> ground, you have to work through the entire route and work this way on
> all signals, which is avoidable. In my stackup, this entire work is
> eliminated.
>
> My methodology is to keep things simple. There is no need to create a
> concern and then solve it.
>
> Regards,
> Prasad
>
> ________________________________
> From: wjcsongr@xxxxxxxxxxxxxxxxxxx [mailto:wjcsongr@xxxxxxxxxxxxxxxxxxx]
> Sent: Monday, July 28, 2008 2:55 PM
> To: Mangipudi, Prasad
> Cc: 'SI LIST'; 'si-list-bounce@xxxxxxxxxxxxx'; 'sunil
> bharadwaz'
> Subject: RE: [SI-LIST] Re: 12 Layer stack
>
>
> Prasad,
>
> I agree with the GROUND assertion if you are going through a connector
> but even then with a few well placed capacitors (assuming we're not in
> Terahertz freq range) can mitigate most of your concerns with the
> voltage plane. As long as there is a good path
> somehow, I think you're
> in good shape. On a design at a different company, we did 800-1200Mhz
> single ended with misreferencing caps at the connector boundaries with
> the signals referenced to power that didn't pass through the connector.
>
> I guess my main point is, rules of thumb should be applied carefully;
> not all rules apply everywhere. I'm sure Dr. Johnson or Dr. Bogatin or
> any other pro would agree with that statement, as most of here would as
> well.
>
> I've done it both ways Prasad and have had 100% success with
> power-signal-ground or ground-signal-ground referencing on hundreds of
> cards, assuming you design for the return paths. Given a choice, I would
> take 4 striplines instead of 2 strips and 2 dual strips. There's nothing
> wrong with your stack, I've done that myself as well. I guess it's just
> a personal preference.
>
> Regards,
>
> Bill
>
> William Csongradi
> Senior Electrical
> Engineer
> Rockwell Collins Heads Down Display Center
> 319-295-7884
>
> Mailing Address
> Rockwell Collins
> 400 Collins Road NE
> MS 105-167
> Cedar Rapids, Iowa 52498-0001
>
>
>
>
> "Mangipudi, Prasad" <Prasad_Mangipudi@xxxxxxxxxxx>
>
> 07/28/2008 04:29 PM
>
> To
> "'wjcsongr@xxxxxxxxxxxxxxxxxxx'"
> <wjcsongr@xxxxxxxxxxxxxxxxxxx> cc 'SI
> LIST' <si-list@xxxxxxxxxxxxx>,
> "'si-list-bounce@xxxxxxxxxxxxx'"
> <si-list-bounce@xxxxxxxxxxxxx>, 'sunil bharadwaz'
> <sunil_bharadwaz@xxxxxxxxx> Subject
> RE: [SI-LIST] Re: 12 Layer stack
>
>
>
>
>
> Bill,
>
> The original question is a general one without details and the 133MHz
> speed is not very high. The suggested stackup keep things simple. Even
> both of the original two stackups can be made to work, with extra
> effort.
>
> By referencing all signals to continuous ground planes, there is no need
> to keep track of return
> signal path for any signal assuming all the
> ground planes are stitched together nicely. This is not true if the
> signals are referenced to power planes.
>
> Dual strip line crosstalk: I have advised increasing the distance
> between the signal layers and/or power planes to adjust for the board
> thickness. By following orthogonal routing on adjacent signal layers,
> crosstalk is minimized. You can also reduce the crosstalk by decreasing
> the dielectric thickness between signal layer and ground plane. The
> signals are coupled more strongly to the reference plane than to other
> signal layer.
>
> Power planes: The power planes may look adjacent, but they are more
> strongly coupled to the adjacent ground planes than to each other.
> Also, most of the current devices need multiple power inputs and by
> localization of power pours, the coupling between them can be made far
> less compared to the coupling to the ground. Those G/P
> pairs can be
> thin dielectric materials if required.
>
> I have used the suggested stackup on many different designs for PCIe,
> DDR2, SAS, SATAI/II, Gigabit Ethernet, FC and never had to worry about
> EMI/EMC, Noise and crosstalk. The stackup alone will not solve all
> issues, but is a starting point for good design. I do not see any
> limitation in the proposed stackup. The devices I have used needed
> multiple power supplies and the best place for decoupling caps had
> always been back of the BGA in my case. I could carve out multiple local
> power pours on the power planes and if required even on signal layers.
>
> -Prasad
>
>
> ________________________________
> From: wjcsongr@xxxxxxxxxxxxxxxxxxx [mailto:wjcsongr@xxxxxxxxxxxxxxxxxxx]
> Sent: Monday, July 28, 2008 1:40 PM
> To: Mangipudi, Prasad
> Cc: 'SI LIST'; si-list-bounce@xxxxxxxxxxxxx; 'sunil bharadwaz'
> Subject: Re: [SI-LIST] Re: 12 Layer
> stack
>
>
> All,
>
> Another interesting topic to get the list fired up with discussion.
>
> Prasad, please explain why you think referencing all signals to GND is a
> good thing? And why coupling power planes of different noise levels in
> the middle of this mess is a good thing?
>
> Our Intel friends can certainly point to the now famous paper about this
> GND referencing stuff. I believe we will discover that as always, rules
> of thumb must be applied with care and not willy nilly everywhere.
>
> I'm very interested in the comments on this one.
>
> I would probably vote to minimize dual stripline wiring to minimize
> xtalk. With the stack below, you'll still have 4 good easily controlled
> wiring layers, 2 on top and bottom for fan out. And you can stick a hunk
> of that buried capacitance stuff in the middle. 'P' in the stack is
> plane. I don't care, except in the middle, if it's power or GND. With
> any stack
> discussed so far, you really only get 4 good layers.
>
> S-G-S-P-S-G-P-S-G-S-G-S.
>
> If that dual strip doesn't bother you, go for A.
>
> Also, doesn't the final answer depend on how many power planes you will
> need in your design? If you're a 10W board, for example, maybe one power
> layer is sufficient. There's that Ohm's law thing again: - )
>
> Regards,
>
> Bill
>
> William Csongradi
> Senior Electrical Engineer
> Rockwell Collins Heads Down Display Center
> 319-295-7884
>
> Mailing Address
> Rockwell Collins
> 400 Collins Road NE
> MS 105-167
> Cedar Rapids, Iowa 52498-0001
>
>
>
> "Mangipudi, Prasad" <Prasad_Mangipudi@xxxxxxxxxxx> Sent by:
> si-list-bounce@xxxxxxxxxxxxx
>
> 07/28/2008 03:19 PM
>
> To
> 'sunil bharadwaz' <sunil_bharadwaz@xxxxxxxxx>, 'SI LIST'
> <si-list@xxxxxxxxxxxxx> cc Subject [SI-LIST] Re: 12 Layer stack
>
>
>
>
>
>
>
> Sunil,
>
> Neither. I
> would use S/G/S/S/G/P/P/G/S/S/G/S to simplify the design.
> All signals reference to ground. Required board thickness is achieved
> by increasing the dielectric between power planes and/or signal planes.
>
> -Prasad
>
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
> On Behalf Of sunil bharadwaz
> Sent: Monday, July 28, 2008 11:08 AM
> To: SI LIST
> Subject: [SI-LIST] 12 Layer stack
>
>
> Hi ,
>
>
>
> I have following two stack up's
>
>
>
> Stack 'A'
>
>
>
> 1)Signal
>
> 2)PWR
>
> 3)GND
>
> 4)Signal
>
> 5)PWR
>
> 6)Signal
>
> 7)Signal
>
> 8)Gnd
>
> 9)Signal
>
> 10)PWR
>
> 11)GND
>
> 12)Signal
>
>
>
> Stack
> 'B'
>
>
>
> 1)Signal
>
> 2)GND
>
> 3)Signal
>
> 4)Signal
>
> 5)Ground
>
> 6)Power
>
> 7)Power
>
> 8)GND
>
> 9)Signal
>
> 10)Signal
>
> 11)PWR
>
> 12)Signal
>
>
>
> Intent is to use one of these stacks for an FPGA based high speed Design
> (Max
> 133 Mhz).
>
> Can i know which one is preferable.
>
>
>
>
>
> regards
>
> Sunil.B
>
>
>
>
>
>
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