[SI-LIST] Re: 10-Layer Stack up
- From: steve weir <weirsi@xxxxxxxxxx>
- To: tmcgonigle@xxxxxxxx, sunil_bharadwaz@xxxxxxxxx, si-list@xxxxxxxxxxxxx
- Date: Mon, 23 May 2005 11:55:29 -0700
Thomas, contrary to popular folklore, the main benefit of a thin sandwich
is not more capacitance but lower inductance.
If you have any doubts, consider that with a high Er dielectric you could
achieve equivalent plane cavity capacitance with a much thicker dielectric
but also much higher inductance. I believe that if you model that, it will
become clear to you that Larry Smith's battle cry: "It's the inductance
stupid!" is on the mark.
It is low inductance that presents a low impedance to high
frequencies. The planes present a lower inductance than the bypass
capacitors, but for it to be useful as a shunt on its own through the
cavity capacitance, you have to cross the AR created by the cavity with the
discrete bypass capacitors. Because of the problems that presents we have
seen many proposals to try and find better damping, whether it be any of
the resistive techniques or high ESR capacitors that Istvan has proposed,
or raising the net ESR of the discrete network using Larry's F^N
technique. Since by and large most people do not use any of the techniques
either Istvan or Larry have proposed to solve that problem, they live with
it for better or for worse. Under those conditions, more capacitance can
be as much of a problem as it can be a benefit. But lower inductance helps
no matter what.
Steve.
At 06:14 AM 5/23/2005 -0700, Thomas McGonigle wrote:
>Sunil,
>
>You might want to put the power and ground planes next to each other, making a
>"sandwich". This created an embedded bypass capacitor, and also lowers the
>spreading inductance of the planes, both of which reduce switching noise at
>high frequencies. See the Xilinx Virtex-4 PCB Designer's guide, pages 35 to
>37. You can find it at : http://www.xilinx.com/bvdocs/userguides/ug072.pdf
>
>
>--- steve weir <weirsi@xxxxxxxxxx> wrote:
> > Sunil, see any of the previous comments about managing cavities.
> >
> >
> > Steve.
> > At 08:09 PM 5/22/2005 -0700, sunil bharadwaz wrote:
> > >Hi All ,
> > >We are trying to design a board with FPGA's.
> > >We are having two Virtex-4 devices on the board.The
> > >max intended speed will be 130 Mhz.This is a ten
> > >layer,50 ohms controlled impedance board.
> > >The high speed signals have been routed in the Layers
> > >3,4,7,8.
> > >We have come up with a stack up as follows.
> > >I have also attached the stack up details as a word
> > >doc.
> > >
> > >I'am looking for some
> > >improvements/concerns/suggestions on the Shown stack
> > >up.Any feed back would be highly appreciated.
> > >
> > > Thanks in advance
> > >
> > > Best Regards
> > > Sunil
> > >
> > >
> > >0.0325 Copper plating layer 1 5.468 mil trace width 50
> > >ohms single ended
> > >0.0175 Copper foil layer 1
> > >0.0940 Prepreg 1-2
> > >0.0350 Copper foil layer 2 plane ---GND
> > >0.1524 Core 2-3
> > >0.0350 Copper foil layer 3 6.278 mil trace width 50
> > >ohms single ended
> > >0.1194 Prepreg 3-4
> > >0.0350 Copper foil layer 4 6.278 mil trace width 50
> > >ohms single ended
> > >0.1524 Core 4-5-6
> > >0.0350 Copper foil layer 5 plane---Power Plane (3.3
> > >Volts I/O)
> > >0.2032 Prepreg 5-6
> > >0.0350 Copper foil layer 6 plane----GND
> > >0.1524 Core 6-7
> > >0.0350 Copper foil layer 7 6.278 mil trace width 50
> > >ohms single ended .
> > >0.1194 Prepreg 7-8
> > >0.0350 Copper foil layer 8 6.278 mil trace width 50
> > >ohms single ended
> > >0.1524 Core 8-9
> > >0.0350 Copper foil layer 9 plane------- Power Plane
> > >(2.5 Volts split plane )
> > >0.0940 Prepreg 9-10
> > >0.0175 Copper foil layer 10
> > >0.0325 Copper plating layer 10 5.468 mil trace width
> > >50 ohms single ended
> > >1.6195 Total PCB thickness in mm
> > >
> > >
> > >
> > >Yahoo! Mail
> > >Stay connected, organized, and protected. Take the tour:
> > >http://tour.mail.yahoo.com/mailtour.html
> > >
> > >
> > >-- Binary/unsupported file stripped by Ecartis --
> > >-- Type: application/msword
> > >-- File: stack1.doc
> > >-- Desc: 354396701-stack1.doc
> > >
> > >
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>
>Thomas E. McGonigle
>8305 48 th Avenue
>College Park, MD 20740
>tmcgonigle@xxxxxxxx
>301-441-1175
>
>
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