[SI-LIST] 100MHz clock rate for PCI-e

  • From: piyush bhatt <piyush.nithmr@xxxxxxxxx>
  • To: si-list@xxxxxxxxxxxxx
  • Date: Fri, 13 May 2011 12:36:14 +0530

Why we use 100Mhz as clock Frequency  for PCI-e operating at much
higher Frequency?
I think they multiple 100MHz clock to high frequency needed to
generate data at high Frequency /use Clock recovery mechanism to
generate clock from data itself.
Is it only because of we want to avoid using extra high frequency pad
for clock, extra pins in connector which should support high frequency
and extra trace to worry about?
Is it impossible to meet clock accuracy and jitter requirement if we
give clock from outside at clock rate equal to data rates?
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