Why we use 100Mhz as clock Frequency for PCI-e operating at much higher Frequency? I think they multiple 100MHz clock to high frequency needed to generate data at high Frequency /use Clock recovery mechanism to generate clock from data itself. Is it only because of we want to avoid using extra high frequency pad for clock, extra pins in connector which should support high frequency and extra trace to worry about? Is it impossible to meet clock accuracy and jitter requirement if we give clock from outside at clock rate equal to data rates? ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List technical documents are available at: http://www.si-list.net List archives are viewable at: //www.freelists.org/archives/si-list Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu