[SI-LIST] Re: 10 Layer Stack-up board/TWR PCB
- From: Rick Collins <gnuarm.2006@xxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Wed, 02 Nov 2011 14:33:48 -0400
I must have missed something. The stackup I saw
only had two ground planes and two power planes.
The part that really gets me is that I never see
the posts from Lee Ritchey. I've tried talking
to the admin and am told the problem must be at
my end. But there is no more reason for that
than it being anywhere else. I've checked the
spam filters and no mesages are being caught
there. It seems to be pretty consistent that I
never get a direct post to the group from Lee. I
don't know if his are the only messages I don't
get. I don't read every message or thread in detail.
Rick
At 09:49 PM 11/1/2011, you wrote:
>There are a lot of ground planes, but this is a conservative design. I
>like conservative designs to get the product out without delays and
>minimum risk. Afterwards one can optimize the design, an you can get
>"kudos" from the boss for discovering a cost reduction!
>
>If the board has many layers and one wants to go from a signal layer
>high in the stack-up to a layer low in the stack-up, if the signals are
>referenced to ground planes then one can via the ground planes together
>close to the signal via and "short out" the interplane Z-axis impedances
>(except for the via impedance itself).
>
>There is no unique solution, its just a matter of how much the enclosure
>need to shield both incoming and exiting energy. As you only need the
>tiniest fraction of the signal energy of most signals to create an EMC
>problem and since the peak values of ESD are so large (only the tiniest
>fraction of the ESD energy will corrupt signals) it is possible to have
>great signal integrity but still have these other problems. Therefore I
>like conservative designs.
>
>Doug
>
>On 11/1/11 12:27 PM, Lee Ritchey wrote:
> > Way too many ground planes.
> >
> > --------------------------------------------------
> > From: "Jory McKinley"<jory_mckinley@xxxxxxxxx>
> > Sent: Tuesday, November 01, 2011 9:02 AM
> > To: "Filion, Marc-Andre"<marc-andre.filion@xxxxxxxxxxxxxx>
> > Cc:<si-list@xxxxxxxxxxxxx>
> > Subject: [SI-LIST] Re: 10 Layer Stack-up board/TWR PCB
> >
> >> My post are showing up either without content or partial? Hopefully this
> >> one post correctly. This is the stack-up I would consider for Jayasuryan
> >> board:
> >>
> >> TOP
> >>
> >> GND
> >> DVDD1_2/D2VDD1_2/DVDD1_8
> >>
> >> GND
> >>
> >> SIG1/SIG2
> >>
> >> SIG3/SIG4
> >>
> >> GND
> >>
> >> DVDD5/DVDD3_3
> >>
> >> GND
> >>
> >> BOTTOM
> >>
> >>
> >> Regards,
> >> -Jory
> >>
> >>
> >>
> >> From: "Filion, Marc-Andre"<marc-andre.filion@xxxxxxxxxxxxxx>
> >> To: Jory McKinley<jory_mckinley@xxxxxxxxx>
> >> Cc: si-list@xxxxxxxxxxxxx
> >> Sent: Tuesday, November 1, 2011 10:45 AM
> >> Subject: RE: [SI-LIST] Re: 10 Layer Stack-up board/TWR PCB
> >>
> >> Hi,
> >> I've always heard that it's a golden rule to have a symmetrical and
> >> balanced stackup, is it just a solid myth or does it have solid roots?
> >> Is it possible to have a non-balanced PCB? Does the dielectric must be
> >> also balanced or just the copper layer?
> >> What are the impact of having an unbalanced stackup?
> >>
> >> Best regards,
> >>
> >> Marc-André Filion | Hardware designer | Kontron Canada | T 450 437 5682
> >> x2243 | E marc-andre.filion@xxxxxxxxxxxxxx
> >>
> >> Kontron Canada Inc
> >> 4555 Rue Ambroise-Lafortune
> >> Boisbriand (Québec) J7H 0A4
> >>
> >> The information contained in this document is confidential and property of
> >> Kontron Canada Inc. Any unauthorized review, use, disclosure or
> >> distribution is prohibited without express written consent of Kontron
> >> Canada Inc. If you are not the intended recipient, please contact the
> >> sender and destroy all copies of the original message and enclosed
> >> attachments.
> >> -----Message d'origine-----
> >> De : si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] De
> >> la part de Jory McKinley
> >> Envoyé : Monday, October 31, 2011 6:06 PM
> >> À : Jory McKinley; Jayasuryan KG; si-list@xxxxxxxxxxxxx
> >> Objet : [SI-LIST] Re: 10 Layer Stack-up board/TWR PCB
> >>
> >> This is a better baanced stack!
> >>
> >>
> >>
> >>
> >> -JOry
> >>
> >>
> >> ________________________________
> >> From: Jory McKinley<jory_mckinley@xxxxxxxxx>
> >> To: Jory McKinley<jory_mckinley@xxxxxxxxx>; Jayasuryan KG
> >> <suryan_tvm@xxxxxxxxxxx>; "si-list@xxxxxxxxxxxxx"<si-list@xxxxxxxxxxxxx>
> >> Sent: Monday, October 31, 2011 3:23 PM
> >> Subject: [SI-LIST] Re: 10 Layer Stack-up board/TWR PCB
> >>
> >>
> >> retrun = return
> >>
> >> and another typo PWR/SIG on lower layer needs swapped better decoupling
> >> loop.
> >>
> >> TOP
> >>
> >> GND1
> >>
> >> DVDD1_2/D2VDD1_2/DVDD1_8
> >>
> >> GND
> >>
> >> SIG1/SIG2
> >>
> >> GND
> >>
> >> SIG3/SIG4
> >>
> >> GND
> >>
> >> DVDD5/DVDD3_3
> >>
> >> BOTTOM
> >>
> >> -Jory
> >>
> >>
> >>
> >> From: Jory McKinley<jory_mckinley@xxxxxxxxx>
> >> To: Jayasuryan KG<suryan_tvm@xxxxxxxxxxx>; "si-list@xxxxxxxxxxxxx"
> >> <si-list@xxxxxxxxxxxxx>
> >> Sent: Monday, October 31, 2011 1:53 PM
> >> Subject: [SI-LIST] Re: 10 Layer Stack-up board/TWR PCB
> >>
> >>
> >> I would consider better power/gnd return, keep in mind loop inductance to
> >> appropriate power (TOP/BOTTOM) placement, you can swap power planes where
> >> needed. This will reduce retrun path discontinuity and potential cavity
> >> resonance. Make sure to include z-axis via retrun stitching.
> >>
> >> TOP
> >>
> >> GND1
> >>
> >> DVDD1_2/D2VDD1_2/DVDD1_8
> >>
> >> GND
> >>
> >> SIG1/SIG2
> >>
> >> GND
> >>
> >> DVDD5/DVDD3_3
> >>
> >> GND
> >>
> >> SIG3/SIG4
> >>
> >> BOTTOM
> >>
> >> -Jory
> >>
> >>
> >> From: Jayasuryan KG<suryan_tvm@xxxxxxxxxxx>
> >> To: si-list@xxxxxxxxxxxxx
> >> Sent: Monday, October 31, 2011 12:39 PM
> >> Subject: [SI-LIST] 10 Layer Stack-up board/TWR PCB
> >>
> >> Dear Experts,
> >>
> >>
> >> I have a question regarding my Through Wall Radio(TWR) PCB. My stack-up is
> >> as follows.
> >>
> >>
> >>
> >> TOP
> >>
> >> GND1
> >>
> >> SIG1/DVDD1_8
> >>
> >> SIG2/DVDD1_2
> >>
> >> PWR1/DVDD3_3
> >>
> >> PWR2/DVDD5
> >>
> >> SIG3/D2VDD1_2
> >>
> >> SIG4/DVDD5
> >>
> >> GND2
> >>
> >> BOTTOM
> >>
> >>
> >>
> >> Max current in this board is less than 1A and interfaces like ADC,DAC and
> >> video signals.
> >>
> >> Also my RF interfaces are going on the top portion of the board, which is
> >> completely isolated form others and running under GND plane. (find the
> >> link for pictures)
> >>
> >>
> >>
> >>
> https://picasaweb.google.com/104062213607119029710/October312011#5669711738723806994
> >>
> >>
> https://picasaweb.google.com/104062213607119029710/October312011#5669711807720941682
> >>
> >>
> >>
> >> I am wondering is there any issue, if I split the power planes like the
> >> above layer stack-up? Or any can give better suggestions!
> >>
> >>
> >>
> >> Looking for your valuable help.
> >>
> >>
> >>
> >> Best Regards,
> >>
> >> - Jayasuryan
> >>
> >>
> >>
> >>
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>--
>-------------------------------------------------------
> ___ _ Doug Smith
> \ / ) P.O. Box 1457
> ========= Los Gatos, CA 95031-1457
> _ / \ / \ _ TEL/FAX: 408-356-4186/358-3799
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