[SI-LIST] Re: 10 Layer PCB Stack-up
- From: "Moody, Emory" <EmoryMoody@xxxxxxxxxxxxxxx>
- To: steve weir <weirsi@xxxxxxxxxx>, Jaison Fernandez <jaisonfernandez@xxxxxxxxx>
- Date: Thu, 13 May 2010 16:31:19 -0400
So I am understanding correctly, this is for 10 layer stack up?
Emory Moody
Sr. Recruiter
SourceRight Solutions
(Partnering with Intel Corporation)
Talent Acquisition Outsourcing
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emorymoody@xxxxxxxxxxxxxxx
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of steve weir
Sent: Thursday, May 13, 2010 3:35 PM
To: Jaison Fernandez
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: 10 Layer PCB Stack-up
Jaison, your stack-up will have poor impedance control and substantial
cross-talk between L1 and L2, and L9 and L10. It is also unbalanced
which makes it susceptible to warpage. Depending on your power
requirements, an alternate 10 layer would be:
1. S1
2. Gnd
3. S2
thick dielectric
4. S3 - low edge rate / frequency
5. Power
dielectric 3-4 mils
6. Gnd
7. S4
thick dielectric to match L3/L4
8. S5
9. Gnd
10. S6.
This gives you good impedance control, and Gnd referencing on S1, S2,
S4, S5, and S6. The disadvantage is the long Z axis run to the power
cavity which will require more bypass caps to compensate. That assumes
that the Z axis inductance isn't so high that they can't. If the power
distribution needs to be near the top for Z axis inductance, you will
either need to come up with enough Cu on L1, and/or L3 to make that
work, go to 12 layer construction, or lose signal layers.
Steve.
Jaison Fernandez wrote:
> Dear All,
> Currently I am working on a board which contains ATMEL AT91SAM9M10, 128MB
> SDRAM (166MHz), GPS Chip solution, High current motor Drivers etc.
>
> I got a 10 Layer reference stack up from team my team as follows:
>
> 1. Top - Signal 1 (Low frequency)
> -------------------------
> 2. Signal 2 (Low frequency)
> -------------------------
> 3. GND 1(Plane)
> -------------------------
> 4. Power 1 (Plane)
> -------------------------
> 5. GND 2 (Plane)
> -------------------------
> 6. Signal 3 (High Frequency)
> -------------------------
> 7. Signal 4 (High Frequency)
> -------------------------
> 8. GND 3 (Plane)
> -------------------------
> 9. Signal 5 (Low frequency)
> -------------------------
> 10. Bottom Signal 6 (Low frequency)
> -------------------------
>
> My major intention is to reduce the radiated emission so that my GPS Chip
> solution using passive antenna should work with out any interference from
> other sections of my board it's self.
>
> Also we need to pass the EMI/EMC tests.
>
> When I refer regarding layer stack up in internet what I can found is all
> signal layers are followed by a immediate reference plane.
>
> Is my above layer stack up is ok for my requirements?
> Experts suggest please...
>
> Regards,
> Jaison Fernandez
>
>
>
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--
Steve Weir
IPBLOX, LLC
150 N. Center St. #211
Reno, NV 89501
www.ipblox.com
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