[SI-LIST] Re: 10 Layer PCB Stack-up
- From: wolfgang.maichen@xxxxxxxxxxxx
- To: "Jaison Fernandez" <jaisonfernandez@xxxxxxxxx>
- Date: Thu, 13 May 2010 12:32:29 -0700
Hello Jaison,
I can see a few issues with your proposed stackup right away.
First, the stackup is not symmetric with regards to the distribution of
GND an power planes. This can cause the board to warp during
manufacturing, since you have much more copper area on one end of the
stackup than on the other (GND/Power planes tend to have much more copper
than signal planes). So something like
S-S-G-S-G-P-S-G-S-S
would be much better in that respect.
Second, you have two high-speed signal layers with no ground or power
plane between them. While sometimes this is done to cut down the layer
count, it makes your life much more difficult: You need to route lines at
90 degrees (one layer vertical, one horizontal) to avoid excessive
crosstalk - and even then you'll still get some. Better to have every
high-speed signal layer sandwiched between two reference planes. Note that
you can use power planes as reference planes as well (not only ground
planes), but risk having power supply noise coupling into your signals.
(you'll also need to supply a signal return path between power and ground,
i.e. add sufficient decoupling).
Finally, just because signals are denoted "slow speed" does not mean they
cannot radiate excessively. It all depends on what the signal rise times
are (not the clock frequency); so a 1 MHz data rate signal with rise times
of 100ps can radiate a lot and you would be advised to move that inside
the board rather than leaving it on the surface. I don't know what the
rise times of your slow speed signals are, but this is a point worth
checking if you are concerned about EMI limits.
Hope that gives you some ideas
Wolfgang
"Jaison Fernandez" <jaisonfernandez@xxxxxxxxx>
Sent by: si-list-bounce@xxxxxxxxxxxxx
05/13/2010 12:17 PM
To
<si-list@xxxxxxxxxxxxx>
cc
Subject
[SI-LIST] 10 Layer PCB Stack-up
Dear All,
Currently I am working on a board which contains ATMEL AT91SAM9M10, 128MB
SDRAM (166MHz), GPS Chip solution, High current motor Drivers etc.
I got a 10 Layer reference stack up from team my team as follows:
1. Top - Signal 1 (Low frequency)
-------------------------
2. Signal 2 (Low frequency)
-------------------------
3. GND 1(Plane)
-------------------------
4. Power 1 (Plane)
-------------------------
5. GND 2 (Plane)
-------------------------
6. Signal 3 (High Frequency)
-------------------------
7. Signal 4 (High Frequency)
-------------------------
8. GND 3 (Plane)
-------------------------
9. Signal 5 (Low frequency)
-------------------------
10. Bottom Signal 6 (Low frequency)
-------------------------
My major intention is to reduce the radiated emission so that my GPS Chip
solution using passive antenna should work with out any interference from
other sections of my board it's self.
Also we need to pass the EMI/EMC tests.
When I refer regarding layer stack up in internet what I can found is all
signal layers are followed by a immediate reference plane.
Is my above layer stack up is ok for my requirements?
Experts suggest please...
Regards,
Jaison Fernandez
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