[SI-LIST] 10 Layer PCB Stack-up
- From: "Jaison Fernandez" <jaisonfernandez@xxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Fri, 14 May 2010 00:47:42 +0530
Dear All,
Currently I am working on a board which contains ATMEL AT91SAM9M10, 128MB
SDRAM (166MHz), GPS Chip solution, High current motor Drivers etc.
I got a 10 Layer reference stack up from team my team as follows:
1. Top - Signal 1 (Low frequency)
-------------------------
2. Signal 2 (Low frequency)
-------------------------
3. GND 1(Plane)
-------------------------
4. Power 1 (Plane)
-------------------------
5. GND 2 (Plane)
-------------------------
6. Signal 3 (High Frequency)
-------------------------
7. Signal 4 (High Frequency)
-------------------------
8. GND 3 (Plane)
-------------------------
9. Signal 5 (Low frequency)
-------------------------
10. Bottom Signal 6 (Low frequency)
-------------------------
My major intention is to reduce the radiated emission so that my GPS Chip
solution using passive antenna should work with out any interference from
other sections of my board it's self.
Also we need to pass the EMI/EMC tests.
When I refer regarding layer stack up in internet what I can found is all
signal layers are followed by a immediate reference plane.
Is my above layer stack up is ok for my requirements?
Experts suggest please...
Regards,
Jaison Fernandez
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