[SI-LIST] Re: 0306 Capacitors

  • From: "Jeremy Plunkett" <jeremy@xxxxxxxxxxxxxxx>
  • To: "steve weir" <weirsp@xxxxxxxxxx>,"Istvan NOVAK" <istvan.novak@xxxxxxxxxxxxxxxx>,leeritchey@xxxxxxxxxxxxx, Farah.Haddadin@xxxxxxxxx,"Ken Patterson" <pattken@xxxxxxxxxxxxxxxxxx>, si-list@xxxxxxxxxxxxx
  • Date: Mon, 15 Mar 2004 19:27:13 -0800

Hi Steve,
Your ascii art may have gotten a bit tweaked due to different fonts so let
me copy it back rotated 90deg:

---------
8=[   ]=8
---------

The "8" represents the via pair at each end of the cap pkg.  The "=" is the
gap between the pads.  The "-" is the outer edge of the cap pads. The
   ]" is the cap body, the terminals are along the entire length of the top
and bottom edges.

I contend that it's important for the width of the gap between pads to be
minimized, with the same minimum spacing maintained from the vias all the
way underneath the cap body from end to end.  And of course the distance of
the vias from the ends of the cap and the spacing between the vias should be
at the minimum possible values given the manufacturing rules.

You could leave a via or 2 at the outside edges of the pads where they were
before but I don't think their presence will make much difference.

Istvan's vias-between-the-pads suggestion is definitely going to give the
best performance for this type of cap, but I think there will be extra costs
associated with both the spacing rules and the vias placed under the cap
that make this too expensive for most applications.

BTW, Istvan also suggested this same layout with the vias at the ends.  You
may want to get his suggestions as well before you actually put this on a
test board.

Jeremy








-----Original Message-----
From: steve weir [mailto:weirsp@xxxxxxxxxx]
Sent: Saturday, March 13, 2004 1:30 AM
To: Jeremy Plunkett; Istvan NOVAK; leeritchey@xxxxxxxxxxxxx;
Farah.Haddadin@xxxxxxxxx; Ken Patterson; si-list@xxxxxxxxxxxxx
Subject: RE: [SI-LIST] Re: 0306 Capacitors


Jeremy, let's make certain that we are talking about the same things
here.  As far as the vertical via tubes are concerned, we agree that closer
makes for tighter coupling the mutual L, and less Lleakage.  If those are
the edges you are referring to, then we are in good agreement.  That effect
is well demonstrated to help both the IDCs and X2Ys.

My comment about the centroid is of the component pad.  As we move vias
away from that pad center, the partial L due to the surface trace
increases.  This is why I believe that pads at the end of the component pad
long axis will provide limited benefit.  But, if we want to go from
intuition to fact we can model and build the thing and see how it
does.  Just to be clear, the way I read your proposal, you would like to:

  +    -
+p   p-
+p   p-
+p   p-
   +   -

Is this what you are suggesting?

With 20/10 via OD/drill for the 0612 reverse geometry part, I can just
squeak by a variation of Istvan's suggestion:

  p+ p
  p  -p
  p+ p
  p  -p

but, unless I retain some vias on the outside will have fewer total
vias.  The deep blue see problem with this is four versus six vias, and if
I add vias to the outside, proximity may well work against me, yielding
poorer results than without any pads on the outside.

Regards,


Steve.

At 07:10 PM 3/12/2004 -0800, Jeremy Plunkett wrote:
>Hi Steve,
>That was the point I was trying to get at, the mutual inductances are
>determined by edge-to-edge distances, not centroid distances, because at
>high frequencies current will crowd to adjacent edges due to proximity and
>skin effects.  I think this is a very strong effect, much more significant
>than most people realize.  This is why pad layouts connecting a surface
>shape to a buried plane can have much better performance than the ones you
>examined so far as long as all air gap dimensions are minimized.
>
>regards,
>Jeremy
>
>-----Original Message-----
>From: steve weir [mailto:weirsp@xxxxxxxxxx]
>Sent: Friday, March 12, 2004 6:45 PM
>To: Jeremy Plunkett; Istvan NOVAK; leeritchey@xxxxxxxxxxxxx;
>Farah.Haddadin@xxxxxxxxx; Ken Patterson; si-list@xxxxxxxxxxxxx
>Subject: RE: [SI-LIST] Re: 0306 Capacitors
>
>
>Jeremy, thanks.
>
>Yes those are pretty much the factors, with a caveat that all points on a
>given pad are not the same, and the surface trace air gap is not nearly as
>significant as the via spacing due to mutual L going down the via tubes.
>
>For the partial inductance due to surface pad position, we really need to
>think in terms of the centroid as the reference point.  So I am more
>inclined to expect an improvement with the reverse aspect ratio caps by
>squeezing some vias in-between the pads as Istvan suggests, rather than out
>at the edges, as my intuition is that the cancellation gain from mutual L
>down the via tubes will be more than offset by the additional inductance of
>moving the vias away from the pad centroid on the surface.  But, testing
>intuition is what we have modelling software and experiments for.
>
>
>At 06:01 PM 3/12/2004 -0800, Jeremy Plunkett wrote:
> >Steve,
> >Thanks for your clear presentation of the X2Y measurements.  It's
>refreshing
> >to see actual data brought forth in an SI list discussion.
> >
> >As I understand it, the primary controlling dimensions for the high
> >frequency mounted inductance of a surface mount capacitor are:
> >
> >1) edge-to-edge distance between the GND and VDD terminals on the
>component.
> >2) separation distance (dielectric thickness) between the mounting
> >pads/connection traces and the underlying plane.
> >3) thickness of soldermask on the board(if present under the capacitor)
and
> >insulation overcoat on the capacitor (these add to the height of the
> >capacitor body over the underlying plane).
> >4) air gap spacing between GND and VDD traces on the surface, over the
path
> >from the component terminals to the vias.
> >5) length of outer layer traces connecting the pads to the vias, measured
> >along the adjacent edges of the VDD and GND traces and mounting pads.
> >6) via pitch between GND and VDD vias (actually clearance between edges
of
> >the drill-holes, not center-to-center pitch)
> >
> >I think the performance of the various capacitor types measured could be
> >improved in some cases by further optimization of the via breakout
pattern
> >taking into account factors 4,5, and 6 above.  For example an optimal
> >breakout for the reverse aspect ratio capacitors would be to use a pair
of
> >vias (1 VDD, 1 GND) at each end (the skinny ends) with minimum pitch to
>each
> >other and placed as close as possible to the capacitor body.  A further
> >improvement could be achieved by minimizing the air gap between the VDD
and
> >GND traces and between the pads underneath the capacitor.
> >
> >Similar improvements could probably be achieved by minimizing the trace
air
> >gaps on the X2Y and IDC capacitor pad layouts.  Some of the variation
> >between the X2Y cases of various sizes in your measurements may be due to
> >variations in the trace air gaps and number of connecting vias, rather
than
> >the case size alone.
> >
> >Given that the X2Y is intended to provide minimal mounted inductance, I
am
> >surprised that the spacing between the GND and A/B terminals is as large
as
> >it is.  It seems quite a bit larger than the minimum that
manufacturability
> >concerns would allow, based on the pitch used for IDCs and capacitor
>arrays.
> >Especially on the larger case sizes, a significant improvement in
>inductance
> >could be achieved by reducing the gap spacing between the edges of the
> >terminals (assuming a corresponding reduction is performed on the spacing
> >between the mounting pads and traces).
>
>Well yes and no.  When I first starting working with these I had a similar
>idea.  But it doesn't quite work out as evidenced by the performance of
>"scalloped" parts that are a lot closer to what you describe.  To really
>provide an iron-clad explanation requires a 3D FEA magnetics model of the
>caps, but the way I have explained it to my own satisfaction is that
>centering the G1/G2 terminations provides better cancellation in the device
>by forcing better symmetry.  The inventor, Bill Anthony is the guy to
>really talk to about this.
>
>
>
> >I'd be very interested to see similar measurements of a test board where
>the
> >layers being bypassed are a surface shape with the GND plane immediately
> >underneath.
>
>That is a lot closer to the surface microstrip fixtures used to evaluate
>raw device inductance.  As the impairment due to vias is reduced, we get
>closer and closer to the performance of those raw values.  This benefits
>all low L caps, IDC included, to the detriment of high L, ie ordinary
>geometry caps.
>
>
> >This is typical of situations where X2Y caps might be used on a
> >DDR VTT supply or a PLL power delivery shape.  It hardly seems worth it
to
> >go to the effort of laying out the pads and vias for an X2Y or IDC
> >connecting the top and bottom planes of a 62mil board when the
performance
> >is so strongly bottlenecked by the enormous spacing between the planes.
>The
> >X2Y might be able to replace 3 or more standard 0603 caps based on
mounted
> >inductance, but when the spreading inductance of the planes is included I
> >will still be better off using the 0603s if I have multiple noise sources
> >separated by any significant distance on the board, because they can be
> >placed next to each individual noise source rather than at a compromise
> >location in between.
>
>Well that generalization is a lot trickier.  Basically, what we are up
>against is the propagation velocity and impedance of the planes.  If I have
>a high impedance plane structure, like in a 4 layer board AND we remain
>within lambda / 10, then the decaps need to be close enough so that the
>lumped Z which is dominated by the spreading inductance from the component
>attachments to the decaps is low enough to satisfy the target.  If we go
>much over lambda / 10, we are screwed, because the transmission line
>impedance of the planes locks in.
>
>If we use high K material for planes, then the impedance comes down, but so
>does the radius for lambda / 10.
>
>So, where I think you and I can generally agree is that it is pointless if
>we can't get "close enough" with enough decaps to meet the target Z as
>attached.  But, beyond that, I think each case has to be analyzed as part
>of the design process.  The nice thing about the X2Y's or the IDCs for that
>matter is that they allow one to use fewer parts, making it easier to mount
>for a given Z inside a fixed radius.  The more caps it takes to hit Z, the
>harder it is to locate them inside a given circle.
>
>
>Regards,
>
>
>Steve.
>
>
> >regards,
> >
> >Jeremy
> >
> >
> >|>--/\/\/--((((((((()--|>
> >
> >Jeremy Plunkett
> >Signal Integrity Engineer
> >www.serverworks.com
> >
> >|>--/\/\/--((((((((()--|>
> >
> >
> >
> >
> >
> >-----Original Message-----
> >From: si-list-bounce@xxxxxxxxxxxxx
> >[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of steve weir
> >Sent: Thursday, March 11, 2004 6:55 PM
> >To: Istvan NOVAK; leeritchey@xxxxxxxxxxxxx; Farah.Haddadin@xxxxxxxxx;
> >Ken Patterson; si-list@xxxxxxxxxxxxx
> >Subject: [SI-LIST] Re: 0306 Capacitors
> >
> >
> >Istvan, your point on capacitance in a given package versus inductance is
> >very important.  It is a fact that you have often repeated, and is
readily
> >demonstrated.
> >
> >I did not test array capacitors because they do not perform as well as
IDC
> >caps and are still a bit pricey even if they are cheaper than IDCs.  I
can
> >run those result, but it will not change the economics.  Since they do
not
> >perform as well as IDCs, and remain considerably more expensive than
X2Ys,
> >economically they lose to X2Ys.
> >
> >Given that we have multiple device geometries there are only two ways
that
> >I know of to evaluate the parts:
> >
> >1) Test each device in an ICM or microstrip type fixture such that only
the
> >raw characteristics of the part are evident.  This has been done, but
draws
> >the justified criticism that it is not representative of what happens on
a
> >real board.
> >
> >2) Test each device with an attachment optimized for that particular
part,
> >as was done for this report.  For example, the raw ESL of a reverse
> >geometry 0508 is lower than that of an 0612, however once mounted, the
best
> >attachment practices for an 0612 yield better results than the best
> >practices.
> >
> >For the tests to be meaningful it is imperative that the via pattern for
> >each device really show the best possible performance.  To that end, all
> >via patterns are off-grid so as to get the vias as close to the pads as
> >possible.  The impact of moving vias away from the pads by even a few
mils
> >can be very dramatic.
> >
> >I have been careful to try and show each capacitor in the best possible
> >light.  I have another via pattern for the 0612 IDC / array capacitor
> >types, but it is still out at fab.  When the results are back they will
be
> >published along with the rest of the data.  The via issues that help with
> >IDCs / arrays are that they have lots of them, and they are closely
> >spaced.  Lots reduces the attachment inductance, and closely spaced
affords
> >some mutual L to reduce effective mounted inductance.  The flip side of
> >that is that because they are closely spaced, the vias have narrow
> >diameters.  I suspect that if someone were to manufacture a part in a
1014
> >package where 0.032 vias could be abutted right to each pad, a gain of
4dB
> >or better versus 0612 could be realized.  An ordinary array capacitor in
> >such a form would then compete for mounted performance with the 0612 IDC
on
> >four / six layer boards, but not on thin substrates.
> >
> >There is absolutely no point in trying to skew results, as any such
attempt
> >would be easily debunked and it would only serve to damage my reputation.
> >
> >Yes, the X2Y geometry allows a short loop with fewer vias than array
> >capacitors, IDC or otherwise.  Both geometries are high quality designs
> >with about 1/4th the raw inductance of a typical 0603 capacitor at 120pH
> >each. This fact is noted in the presentation.  That level of reduction is
> >not going to come from the pad positions alone as is demonstrated by the
> >fact that as we go larger in X2Ys with pads further apart the inductance
> >goes down, not up.
> >
> >Regards,
> >
> >
> >Steve
> >
> >
> >
> >At 09:19 PM 3/11/2004 -0500, Istvan NOVAK wrote:
> > >Steve,
> > >
> > >Eight and 10-terminal capacitors are also available from multiple
> > >sources, not only from AVX.  Also, similar to the IDC parts, there are
> > >capacitor arrays available in four and eight terminal packages, which
>offer
> > >inductances only slightly higher than IDC parts' inductances.
> > >
> > >You are correct that even if the capacitance was different, the
> > >important parameter is inductance.  To Lee's point: these measured
curves
> > >dont really show apples to apples comparison, because each via pattern
> > >is different.  However, given the fact that the terminal geometry of
>these
> > >capacitors are also different, they cant even have the same via
pattern.
> > >And this could show the strength of the X2Y capacitor in this
>application.
> > >The fact that one of the terminals is in the middle of the body, lends
> > >itself
> > >very well to via placements with small loop size.  While the
> > >field-cancellation
> > >mechanism of the X2Y capacitor may be accessible mostly in
> > >differential connections, when hooked up to planes in single-ended
>manner,
> > >the terminal arrangement of the part appears to be its strength.
> > >
> > >Regards,
> > >
> > >Istvan
> > >
> > >
> > >
> > >----- Original Message -----
> > >From: "steve weir" <weirsp@xxxxxxxxxx>
> > >To: <leeritchey@xxxxxxxxxxxxx>; <Farah.Haddadin@xxxxxxxxx>; "Ken
>Patterson"
> > ><pattken@xxxxxxxxxxxxxxxxxx>; <si-list@xxxxxxxxxxxxx>
> > >Sent: Thursday, March 11, 2004 8:18 PM
> > >Subject: [SI-LIST] Re: 0306 Capacitors
> > >
> > >
> > > > Lee, there is no sleight of hand here.  First, a 56nF X2Y is really
a
> > >112nF
> > > > part.  X2Y parts are rated on the circuit one capacitance.  A 56nF
X2Y
> >has
> > > > two 56nF caps in it, so in a circuit two configuration the
capacitance
> >is
> > > > 112nF.  This is easily seen by the fact that the capacitive portion
of
> >the
> > > > plots line up directly with the 100nF conventional capacitors.
> > > >
> > > > Second, inductance is determined by the capacitor body design, not
the
> > > > capacitance.  We can take virtually any 0603 capacitor and get the
>same
> > > > inductive line.  Once we get significantly past the SRF the
insertion
> >loss
> > > > is equal for all.  Similarly for the X2Y, IDC etc.  The IDC 0.47 is
>what
> > > > was available in stock.  The device still demonstrates very good
ESL,
> >but
> > > > it is impaired by the via pattern.  I have a new via pattern that we
>are
> > > > testing that should improve it somewhat.  Whether the pattern will
>pull
> > >the
> > > > IDC below the X2Y plot or not remains to be seen.
> > > >
> > > > These tests show the real behavior with the capacitors attached to a
> >plane
> > > > without using a plane so large that the anti-resonant peak
interferes
> >with
> > > > measurements well beyond 100MHz.  The tests correlate to models
very,
> >very
> > > > well.  The predicted performance of capacitors came out within 1dB
of
> > > > models made before the tests were run.  If we build a big board,
there
> >is
> > > > not going to be any change in the relative results.  If you disagree
> >with
> > > > this, please indicate the science that would support such an idea.
> > > >
> > > > X2Y's are licensed to five manufacturers at present.  IDC's are an
AVX
> > >only
> > > > option.
> > > >
> > > > No, I fundamentally disagree with your claim about capacitive SRF.
>What
> > > > matters is insertion loss.  The SRF determines where that loss
bottoms
> > >out,
> > > > and Q determines how steep the peak inflection is.  Significantly
>above
> > >the
> > > > SRF, which will be well below 30MHz for any large capacitance versus
> >case
> > > > style we care to choose we will be well past the SRF, and impedance
>and
> > > > therefore insertion loss is determined by the mounted ESL.  This is
a
> > >point
> > > > you can find in your own book in the chapters written by John Zasio.
> > > >
> > > > If you prefer milliohms it is a simple translation of:
> > > >
> > > > 0 dB 25 ohms
> > > > -20dB 2.5 ohms
> > > > -40dB 0.25 ohms
> > > > -60dB 0.025 ohms
> > > >
> > > > Again this you will find in your own book.  We reported dB because
>that
> >is
> > > > exactly what the tests report.
> > > >
> > > > Regards,
> > > >
> > > >
> > > > Steve.
> > > > At 08:51 AM 3/11/2004 -0800, Lee Ritchey wrote:
> > > > >Steve,
> > > > >
> > > > >Looked at the data from X2Y.  Most of the tests use two different
> >values
> > >of
> > > > >capacitor, the value used for the X2Y making it look better.  (IDC
>470
> > >nF,
> > > > >X2Y 56 nF)  (0612 100 nF, X2Y 56 nF)  I could get the same results
>with
> > >the
> > > > >same skewed tests.  Sadly, this is a common problem with vendor
> >furnished
> > > > >data.  Remember Getek?
> > > > >
> > > > >I was really interested in tests you have personally made that
> > >demonstrate
> > > > >true A-B comparisons on a PCB that is representative of a real
power
> > > > >subsystem, as we have done.  What I mean by that is examine
impedance
> >vs.
> > > > >frequency for a PCB with enough plane capacitance to support the
> > >switching
> > > > >transients seen when driving data buses, etc.  When you do that,
you
> >are
> > > > >going to come to the same conclusions that we did- not worth the
>extra
> > > > >resources and not worth forcing your manufacturer to use a single
> >sourced
> > > > >part.
> > > > >
> > > > >   Remember, what counts is the frequency at which the capacitor is
> > >series
> > > > >resonant and that is a combination of the value of C and total ESL.
> >For
> > > > >all of the examples shown it is less than 30 MHz.  Switching
>harmonics
> > > > >usually start abouve 100 MHz.
> > > > >
> > > > >Final comment on the data is the vertical scale is in db.  It would
>be
> >of
> > > > >far greater value if it were in milliohms.  Then we could tell more
> >about
> > > > >what these capacitors do for us in the power subsystem.
> > > > >
> > > > >Lee
> > > > >
> > > > >
> > > > > > [Original Message]
> > > > > > From: steve weir <weirsp@xxxxxxxxxx>
> > > > > > To: <leeritchey@xxxxxxxxxxxxx>; <Farah.Haddadin@xxxxxxxxx>; Ken
> > >Patterson
> > > > ><pattken@xxxxxxxxxxxxxxxxxx>; <si-list@xxxxxxxxxxxxx>
> > > > > > Date: 3/10/2004 3:17:18 PM
> > > > > > Subject: Re: [SI-LIST] Re: 0306 Capacitors
> > > > > >
> > > > > > Lee, the file is available on X2Y's web site, but I have
attached
>it
> > >here
> > > > > > as well.  I spoke with Dave Anthony, dave@xxxxxxx and he will be
> >happy
> > >to
> > > > > > supply you with one of the test boards if you like.
> > > > > >
> > > > > >
> > > > > > Regards,
> > > > > >
> > > > > >
> > > > > > Steve.
> > > > > > At 01:50 PM 3/10/2004 -0800, Lee Ritchey wrote:
> > > > > > >Steve,
> > > > > > >
> > > > > > >How about sharing the actual test results with us?
> > > > > > >
> > > > > > >Lee
> > > > > > >
> > > > > > >
> > > > > > > > [Original Message]
> > > > > > > > From: steve weir <weirsp@xxxxxxxxxx>
> > > > > > > > To: <leeritchey@xxxxxxxxxxxxx>; <Farah.Haddadin@xxxxxxxxx>;
>Ken
> > > > >Patterson
> > > > > > ><pattken@xxxxxxxxxxxxxxxxxx>; <si-list@xxxxxxxxxxxxx>
> > > > > > > > Date: 3/10/2004 10:44:23 AM
> > > > > > > > Subject: [SI-LIST] Re: 0306 Capacitors
> > > > > > > >
> > > > > > > > Lee,  It is all in the coefficients.  There is no magic
here.
>I
> > >have
> > > > >the
> > > > > > > > data carefully taken at the planes themselves and it does
show
> > > > >dramatic,
> > > > > > >as
> > > > > > > > in 3:1 improvement at the planes using X2Y versus 0603.  All
>the
> > >data
> > > > >I
> > > > > > > > have, does in fact correlate well to what you have
published.
> > >While
> > > > >that
> > > > > > > > may seem a contradiction, it is not.
> > > > > > > >
> > > > > > > > What we are dealing with is a simple 1/( M + N ) equation
for
> > > > >admittance
> > > > > > > > where M is the ESL of the discrete device and N is the
partial
> > > > >inductance
> > > > > > > > of the mounting structure and the planes themselves.  As I
> > >suggested a
> > > > > > > > month or two ago, if we take a graphical view of this to
gain
> > > > >intuition,
> > > > > > >we
> > > > > > > > can simply hold M or N constant and plot against the other.
>It
> >is
> > > > >easy
> > > > > > >to
> > > > > > > > confirm that if M >> N, then reductions to N offer little
help
> >and
> > > > > > > > vice-versa.  When dealing with ordinary capacitors with ESLs
>of
> > > > > > >450-500pH,
> > > > > > > > that means that reducing the attachment inductance from
values
> > >much
> > > > >below
> > > > > > > > 1nH show rapidly diminishing returns.   A good two via mount
>on
> >a
> > >four
> > > > > > > > layer 0.062 board yields total inductance of just about
>1200pH.
> > >Here
> > > > >the
> > > > > > > > attachment inductance is not too much bigger than the ESL of
>the
> > > > >device,
> > > > > > > > and as you have experience with, dropping the attachment
> > >inductance
> > > > >by a
> > > > > > > > factor of two only improves the total inductance by less
than
> >1/3
> > >to
> > > > > > >about
> > > > > > > > 850pH, while doubling the number of holes that we have to
>drill.
> > >So,
> > > > >we
> > > > > > > > are only able to exchange primarily parts placement costs
> >against
> > > > >drill
> > > > > > >holes.
> > > > > > > >
> > > > > > > > However, when we take an ESL on the order of 120pH, that
>picture
> > > > >changes
> > > > > > > > completely.  Now, the mounting inductance of 700-750pH is
very
> > > > >dominant,
> > > > > > > > and there are substantial gains to be had by reducing same.
>So,
> > >for
> > > > > > > > example by using a properly designed six via mount for the
>X2Y,
> > >the
> > > > >total
> > > > > > > > mounted inductance drops to 300-400pH depending on just how
> > >aggressive
> > > > > > >you
> > > > > > > > want to get with the vias.  I have test boards you can
measure
> >in
> > >your
> > > > > > >own
> > > > > > > > facilities with repeatable values under 300pH.  That is a
75%
> > > > >reduction
> > > > > > >in
> > > > > > > > parts count, and a 25% reduction in total vias to achieve
the
> >same
> > > > >high
> > > > > > > > frequency impedance AS SEEN AT THE PLANES.
> > > > > > > >
> > > > > > > > Regards,
> > > > > > > >
> > > > > > > >
> > > > > > > > Steve.
> > > > > > > >
> > > > > > > >
> > > > > > > >
> > > > > > > > At 09:01 AM 3/10/2004 -0800, Lee Ritchey wrote:
> > > > > > > > >Steve,
> > > > > > > > >
> > > > > > > > >I have similar tests that show the inductance reduction and
I
> > >agree.
> > > > > > >What
> > > > > > > > >counts is the effect the mounted capacitor has on the
>impedance
> > >of
> > > > >the
> > > > > > > > >power system.  When this test is done, the lowering of the
> > >overall
> > > > > > > > >inductance is visible as a shift to a higher frequency of
the
> > >series
> > > > > > > > >resonance as well as the parallel resonance between the
> >capacitor
> > > > > > >parasitic
> > > > > > > > >inductance and the plane capacitance..  However, in almost
>all
> > >cases
> > > > >this
> > > > > > > > >shift is not large enough to warrant the extra cost of the
>vias
> > >or
> > > > >the
> > > > > > >more
> > > > > > > > >expensive capacitors.
> > > > > > > > >
> > > > > > > > >I hate to mention books, but we have published this data.
>I'll
> > >post
> > > > >it
> > > > > > >on
> > > > > > > > >my web site.  UMR has done similar tests and published the
> > >results
> > > > >in the
> > > > > > > > >IEEE proceedings on EMC.
> > > > > > > > >
> > > > > > > > >Lee
> > > > > > > > >
> > > > > > > > >
> > > > > > > > > > [Original Message]
> > > > > > > > > > From: steve weir <weirsp@xxxxxxxxxx>
> > > > > > > > > > To: <leeritchey@xxxxxxxxxxxxx>;
><Farah.Haddadin@xxxxxxxxx>;
> > >Ken
> > > > > > >Patterson
> > > > > > > > ><pattken@xxxxxxxxxxxxxxxxxx>; <si-list@xxxxxxxxxxxxx>
> > > > > > > > > > Date: 3/9/2004 10:00:18 AM
> > > > > > > > > > Subject: RE: [SI-LIST] Re: 0306 Capacitors
> > > > > > > > > >
> > > > > > > > > > Lee, I have a whole lot of test data that shows big
> > >differences
> > > > > > >between
> > > > > > > > > > normal 0603's, with 2 and four via patterns as well as
> >reverse
> > > > > > >geometry
> > > > > > > > > > caps versus X2Y's.
> > > > > > > > > >
> > > > > > > > > > On a four layer board where the differences will be the
> >least
> > >due
> > > > >to
> > > > > > >the
> > > > > > > > > > dominance of via inductance,  we go from about 1200pH
for
>an
> > >0603
> > > > >with
> > > > > > > > > > 0.050 spaced side mount via's, one per pad, to 850pH
with
> >four
> > > > >vias
> > > > > > > > >total,
> > > > > > > > > > to under 300pH with X2Y 0603 and a optimized via
pattern.
>A
> > >4:1
> > > > > > > > >reduction
> > > > > > > > > > in parts count saves a lot of money.
> > > > > > > > > >
> > > > > > > > > > Nothing is free, the via pattern isn't as friendly as
that
> > > > >convenient
> > > > > > > > > > 0.050" spacing, but the total number of vias needed in
the
> > >board
> > > > >to
> > > > > > >yield
> > > > > > > > > > an impedance at say 100MHz also comes down considerably
> >versus
> > > > >normal
> > > > > > >or
> > > > > > > > > > reverse geometry 0603s.
> > > > > > > > > >
> > > > > > > > > > Steve.
> > > > > > > > > >
> > > > > > > > > > At 09:29 AM 3/9/2004 -0800, Lee Ritchey wrote:
> > > > > > > > > > >Farah,
> > > > > > > > > > >
> > > > > > > > > > >By the time you add in the inductance of the mounting
> > >inductance
> > > > >for
> > > > > > >your
> > > > > > > > > > >PCB, the lower inductance you get with this uncommon
>shaped
> > > > > > >capacitor is
> > > > > > > > > > >not worth it.  Stick with 0603 and use via mounting
pads
>on
> > >the
> > > > > > >sides of
> > > > > > > > > > >the capacitor rather than the end and you get the best
> > >compromise
> > > > > > >between
> > > > > > > > > > >cost, PCB space and performance.  Using multiple vias
>does
> > > > >reduce the
> > > > > > > > > > >mounting inductance some, but is not worth the cost in
> >terms
> > >of
> > > > >PCB
> > > > > > >space
> > > > > > > > > > >and drilling costs.  We've made many controlled tests
to
> > > > >establish
> > > > > > >this.
> > > > > > > > > > >
> > > > > > > > > > >Lee
> > > > > > > > > > >
> > > > > > > > > > >
> > > > > > > > > > > > [Original Message]
> > > > > > > > > > > > From: steve weir <weirsp@xxxxxxxxxx>
> > > > > > > > > > > > To: <Farah.Haddadin@xxxxxxxxx>; Ken Patterson
> > > > > > > > > > ><pattken@xxxxxxxxxxxxxxxxxx>; <si-list@xxxxxxxxxxxxx>
> > > > > > > > > > > > Date: 3/9/2004 6:27:44 AM
> > > > > > > > > > > > Subject: [SI-LIST] Re: 0306 Capacitors
> > > > > > > > > > > >
> > > > > > > > > > > > Farah,
> > > > > > > > > > > >
> > > > > > > > > > > > I believe Murata does make 0306's, but you will get
> >lower
> > > > > > >inductance
> > > > > > > > >at a
> > > > > > > > > > > > much lower price from an 0603 X2Y.  The only caveat
is
> > >that
> > > > >you
> > > > > > >are
> > > > > > > > > > > > presently limited to 200nF in the X2Y, whereas an
0306
> >in
> > >X5R
> > > > >can
> > > > > > > > >support
> > > > > > > > > > > > larger values.  Unmounted an 0306 is about
190-200pH,
> > >whereas
> > > > >an
> > > > > > >0603
> > > > > > > > >X2Y
> > > > > > > > > > > > is about 120pH.
> > > > > > > > > > > >
> > > > > > > > > > > > Regards,
> > > > > > > > > > > >
> > > > > > > > > > > >
> > > > > > > > > > > > Steve.
> > > > > > > > > > > > At 08:16 AM 3/9/2004 -0600, Haddadin, Farah wrote:
> > > > > > > > > > > >
> > > > > > > > > > > > >I tried AVX... They don't make 0306 caps, although
> >their
> > >data
> > > > > > >sheets
> > > > > > > > > > > > >indicate that they do.
> > > > > > > > > > > > >
> > > > > > > > > > > > >Thanks,
> > > > > > > > > > > > >Farah
> > > > > > > > > > > > >
> > > > > > > > > > > > >-----Original Message-----
> > > > > > > > > > > > >From: Ken Patterson
> > >[mailto:pattken@xxxxxxxxxxxxxxxxxx]=20
> > > > > > > > > > > > >Sent: Tuesday, March 09, 2004 8:16 AM
> > > > > > > > > > > > >To: Haddadin, Farah; si-list@xxxxxxxxxxxxx
> > > > > > > > > > > > >Subject: RE: [SI-LIST] 0306 Capacitors
> > > > > > > > > > > > >
> > > > > > > > > > > > >
> > > > > > > > > > > > >Try AVX. They make a line of reverse aspect caps.
> > > > > > > > > > > > >
> > > > > > > > > > > > >Regards,
> > > > > > > > > > > > >
> > > > > > > > > > > > >Ken
> > > > > > > > > > > > >
> > > > > > > > > > > > >-----Original Message-----
> > > > > > > > > > > > >From: Haddadin, Farah
>[mailto:Farah.Haddadin@xxxxxxxxx]
> > > > > > > > > > > > >Sent: Tuesday, March 09, 2004 9:11 AM
> > > > > > > > > > > > >To: si-list@xxxxxxxxxxxxx
> > > > > > > > > > > > >Subject: [SI-LIST] 0306 Capacitors
> > > > > > > > > > > > >
> > > > > > > > > > > > >
> > > > > > > > > > > > >
> > > > > > > > > > > > >Experts,
> > > > > > > > > > > > >
> > > > > > > > > > > > >Does anybody know vendors that can produce 0306
>ceramic
> > > > > > >capacitors?
> > > > > > > > > > > > >
> > > > > > > > > > > > >Thanks,
> > > > > > > > > > > > >Farah
> > > > > > > > > > > >
> > > > > > >
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