[SI-LIST] Re: 0306 Capacitors

  • From: steve weir <weirsp@xxxxxxxxxx>
  • To: jseeger@xxxxxxxxxxxxxx, si-list@xxxxxxxxxxxxx
  • Date: Mon, 15 Mar 2004 10:37:30 -0800

Jeff, let's try this again.  The issue under discussion was whether we 
could lower inductance by increasing via ID.  My point was that for the 
very reasons you state, any increase in the via ID will force us into an 
increase in the OD, and hence the inductance goes up.  If there was excess 
margin to begin with, it just means we placed the via suboptimally with 
excess inductance.

Regards,


Steve.

At 01:11 PM 3/15/2004 -0500, Jeff Seeger wrote:
>steve weir wrote:
> >
> > snip <
> > Is there a good reason that we would not track ID and OD at the
> > economic sweet spot of our fabrication capability?
> >
>
>         Okay, now you guys are scaring me.
>
>         We do realize that the .010" hole can and will appear at
>         any location within that .020" pad, right?   Vendors may
>         even seek to allow breakout (drill partially beyond .020"
>         circle) particularly on a volume run and/or large panel.
>
>         And since I just have to throw this into the soup, please
>         recall thru via pads must remain distinct from the capaci-
>         tor land, with a soldermask dam, at worst case.  With the
>         fine point being put on this analysis, fabrication toler-
>         ances appear quite large.
>
>         Cheers,
>--
>
>       Jeff Seeger                         Applied CAD Knowledge Inc
>       Chief Technical Officer                  Tyngsboro, MA  01879
>       jseeger "at" appliedcad "dot" com                978 649 9800
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