[raspi-internals] Re: Question about opcode 0xE7
- From: Herman Hermitage <hermanhermitage@xxxxxxxxxxx>
- To: "raspi-internals@xxxxxxxxxxxxx" <raspi-internals@xxxxxxxxxxxxx>
- Date: Mon, 23 Sep 2013 14:50:10 +1200
1110 0110 ww 0 d:5 s:5 o:27 ld<w> rd, o(rs)
Load from address rs+o to rd+o
1110 0110 ww 1 d:5 s:5 o:27 st<w> rd, o(rs)
Store from rd to address rs+o
1110 0111 ww 0 d:5 11111 o:27 ld<w> rd, o(pc)
Load pc relative.
1110 0111 ww 1 d:5 11111 o:27 st<w> rd, o(pc)
Store pc relative.
From memory first one hangs/exception if rs=31 (pc)
Second one, I dont recall what happens if a base other than pc is used.
So the second one deals with pipelining issues around pc contents.
----------------------------------------
> From: shacharr@xxxxxxxxx
> Date: Mon, 23 Sep 2013 04:42:27 +0200
> Subject: [raspi-internals] Re: Question about opcode 0xE7
> To: raspi-internals@xxxxxxxxxxxxx
>
> On Mon, Sep 23, 2013 at 5:38 AM, Shachar Raindel <shacharr@xxxxxxxxx> wrote:
>> Hi,
>>
>> I'm looking at the 48 bit opcode that starts with 0xE7. The programmer
>> reference describes it as:
>>
>> 1110 0111 ww 0 d:5 11111 o:27 ld<w> rd, o(pc)
>> Load pc relative.
>> 1110 0111 ww 1 d:5 11111 o:27 st<w> rd, o(pc)
>> Store pc relative.
>>
>> With the .arch file describing it as:
>>
>> 1110 0111 ww0d dddd 1111 1ooo oooo oooo oooo oooo oooo oooo ";
>> ld%s{w} r%i{d}, 0x%08x{$+o} ;(pc)"
>> 1110 0111 ww1d dddd 1111 1ooo oooo oooo oooo oooo oooo oooo ";
>> st%s{w} r%i{d}, 0x%08x{$+o} ;(pc)"
>> 1110 0111 ww0d dddd ssss sooo oooo oooo oooo oooo oooo oooo ";
>> test ld%s{w} r%i{d}, 0x%08x{o}(r%i{s})"
>> 1110 0111 ww1d dddd ssss sooo oooo oooo oooo oooo oooo oooo ";
>> test st%s{w} r%i{d}, 0x%08x{o}(r%i{s})"
>>
>> The weird part here is that opcode 0xE6 already implements load with
>> 27 bit offset relative to arbitrary register, so the 0xE7 variant
>> seems redundant.
>> Based on the context of where I saw 0xE7 instructions, I think it is a
>> memory-indirect load (
>> http://en.wikipedia.org/wiki/Addressing_mode#Memory_indirect ).
>> This means it fetches the value at o(pc), and uses that as the address
>> for the value to fetch into rd.
>>
>> Am I correct in my analysis? Should we update documentation on this?
>
> Just figured out it was a normal indirect load, with me not reading
> the assembly carefully enough.
>
> That leaves the question - what is the difference between 0xE6
> command, and 0xE7 command?
>
> Thanks,
> --Shachar
>
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