[raspi-internals] Interrupt mask registers?

  • From: "Kristina Brooks" <tinab@xxxxxxx>
  • To: raspi-internals@xxxxxxxxxxxxx
  • Date: Tue, 24 May 2016 22:31:44 +0100

Hi,
Does anyone know how VC4's interrupt controller interrupt mask
registers work? There's 8 of them (IC0_MASKn), but I'm not sure how
they work, I've been told they use 4 bits per interrupt to define
priority, with anything other than 0 being unmasked, but I'm not
certain about that. Does anyone know more? Trying to unmask interrupt
#94 which should be the owner 1 mailbox interrupt. Trying to get a
minimal firmware on the VC4 to do "secure" read/writes for the ARM
side.
Thank you. 

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