Re: Separated fetch of bytecode instructions from its decode+dispatch.
- From: Mike Pall <mike-1503@xxxxxxxxxx>
- To: luajit@xxxxxxxxxxxxx
- Date: Sun, 8 Mar 2015 13:02:50 +0100
Gustavo Serra Scalet wrote:
> What would be the reason for that? For readability purposes I'd
> leave them together but as they are separated for some
> architectures, one reason that I can think of is to optimize the
> processor's pipeline in order to avoid idling during the fetch
> of the next instruction. Other processors may have an optimized
> pipeline for this case so they can stick together. Is that so?
> If not, why?!
There are many things to consider when optimizing an interpreter.
Number of registers, early loads, late stores, split and merged
instructions, in-order vs. out-of-order engines or a mix of both.
In fact, a lot of this is the result of experimentation and
benchmarking of different approaches on various hardware platforms.
It depends on which actual hardware one needs to cater for.
IMHO before embarking on a new port, it's mandatory to read all
about the internal architecture of a CPU, including execution
units, pipeline structure, load/store architecture, branch
prediction, latencies and throughput, etc. I don't think that's
something that can be summarized in a couple of sentences.
--Mike
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