[llvm-uc] [PATCH] uc32: Add empty Schedule description
- From: Jia Liu <proljc@xxxxxxxxx>
- To: llvm-uc@xxxxxxxxxxxxx
- Date: Mon, 26 Nov 2012 21:07:35 -0800
Signed-off-by: Jia Liu <proljc@xxxxxxxxx>
---
lib/Target/UniCore/UniCore.td | 1 +
lib/Target/UniCore/UniCoreSchedule.td | 34 +++++++++++++++++++++++++++++++++
2 files changed, 35 insertions(+)
create mode 100644 lib/Target/UniCore/UniCoreSchedule.td
diff --git a/lib/Target/UniCore/UniCore.td b/lib/Target/UniCore/UniCore.td
index 5006b4d..1b919bc 100644
--- a/lib/Target/UniCore/UniCore.td
+++ b/lib/Target/UniCore/UniCore.td
@@ -21,6 +21,7 @@ include "llvm/Target/Target.td"
include "UniCoreRegisterInfo.td"
include "UniCoreInstrInfo.td"
+include "UniCoreSchedule.td"
//===----------------------------------------------------------------------===//
// UniCore processors supported.
diff --git a/lib/Target/UniCore/UniCoreSchedule.td
b/lib/Target/UniCore/UniCoreSchedule.td
new file mode 100644
index 0000000..77a8fc0
--- /dev/null
+++ b/lib/Target/UniCore/UniCoreSchedule.td
@@ -0,0 +1,34 @@
+//===- UniCoreSchedule.td - UniCore Scheduling Definitions -*- tablegen
-*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Functional units across UniCore chips sets, copy from Mips.
+//===----------------------------------------------------------------------===//
+def ALU : FuncUnit;
+
+//===----------------------------------------------------------------------===//
+// Instruction Itinerary classes used for UniCore
+//===----------------------------------------------------------------------===//
+def IIAlu : InstrItinClass;
+def IILoad : InstrItinClass;
+def IIStore : InstrItinClass;
+def IIBranch : InstrItinClass;
+
+def IIPseudo : InstrItinClass;
+
+//===----------------------------------------------------------------------===//
+// UniCore Generic instruction itineraries.
+//===----------------------------------------------------------------------===//
+// http://llvm.org/docs/doxygen/html/structllvm_1_1InstrStage.html
+def UniCoreGenericItineraries : ProcessorItineraries<[ALU], [], [
+ InstrItinData<IIAlu , [InstrStage<1, [ALU]>]>,
+ InstrItinData<IILoad , [InstrStage<3, [ALU]>]>,
+ InstrItinData<IIStore , [InstrStage<1, [ALU]>]>,
+ InstrItinData<IIBranch , [InstrStage<1, [ALU]>]>
+]>;
--
1.7.10.2 (Apple Git-33)
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