[llvm-uc] [PATCH] uc32: Add Register description
- From: Jia Liu <proljc@xxxxxxxxx>
- To: llvm-uc@xxxxxxxxxxxxx
- Date: Mon, 26 Nov 2012 10:10:04 -0800
Mininal TD system
Signed-off-by: Jia Liu <proljc@xxxxxxxxx>
---
.../UniCore/MCTargetDesc/UniCoreMCTargetDesc.cpp | 18 ++++-
.../UniCore/MCTargetDesc/UniCoreMCTargetDesc.h | 5 ++
lib/Target/UniCore/Makefile | 4 +-
lib/Target/UniCore/UniCore.h | 5 ++
lib/Target/UniCore/UniCore.td | 57 ++++++++++++++++
lib/Target/UniCore/UniCoreRegisterInfo.cpp | 37 ++++++++++
lib/Target/UniCore/UniCoreRegisterInfo.h | 37 ++++++++++
lib/Target/UniCore/UniCoreRegisterInfo.td | 72 ++++++++++++++++++++
lib/Target/UniCore/UniCoreTargetMachine.cpp | 9 ++-
lib/Target/UniCore/UniCoreTargetMachine.h | 14 ++--
10 files changed, 249 insertions(+), 9 deletions(-)
create mode 100644 lib/Target/UniCore/UniCore.td
create mode 100644 lib/Target/UniCore/UniCoreRegisterInfo.cpp
create mode 100644 lib/Target/UniCore/UniCoreRegisterInfo.h
create mode 100644 lib/Target/UniCore/UniCoreRegisterInfo.td
diff --git a/lib/Target/UniCore/MCTargetDesc/UniCoreMCTargetDesc.cpp
b/lib/Target/UniCore/MCTargetDesc/UniCoreMCTargetDesc.cpp
index e77f929..dc916e3 100644
--- a/lib/Target/UniCore/MCTargetDesc/UniCoreMCTargetDesc.cpp
+++ b/lib/Target/UniCore/MCTargetDesc/UniCoreMCTargetDesc.cpp
@@ -12,9 +12,25 @@
//===----------------------------------------------------------------------===//
#include "UniCoreMCTargetDesc.h"
+#include "llvm/MC/MCCodeGenInfo.h"
+#include "llvm/MC/MCInstrInfo.h"
+#include "llvm/MC/MCRegisterInfo.h"
+#include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/Support/TargetRegistry.h"
+
+#define GET_REGINFO_MC_DESC
+#include "UniCoreGenRegisterInfo.inc"
using namespace llvm;
-// Force static initialization.
+static MCRegisterInfo *createUniCoreMCRegisterInfo(StringRef TT) {
+ MCRegisterInfo *X = new MCRegisterInfo();
+ InitUniCoreMCRegisterInfo(X, UniCore::PC);
+ return X;
+}
+
extern "C" void LLVMInitializeUniCoreTargetMC() {
+ // Register the MC register info.
+ TargetRegistry::RegisterMCRegInfo(TheUniCoreTarget,
+ createUniCoreMCRegisterInfo);
}
diff --git a/lib/Target/UniCore/MCTargetDesc/UniCoreMCTargetDesc.h
b/lib/Target/UniCore/MCTargetDesc/UniCoreMCTargetDesc.h
index cdce996..49258f4 100644
--- a/lib/Target/UniCore/MCTargetDesc/UniCoreMCTargetDesc.h
+++ b/lib/Target/UniCore/MCTargetDesc/UniCoreMCTargetDesc.h
@@ -22,4 +22,9 @@ class Target;
extern Target TheUniCoreTarget;
} // End llvm namespace
+// Defines symbolic names for UniCore registers.
+// This defines a mapping from register name to register number.
+#define GET_REGINFO_ENUM
+#include "UniCoreGenRegisterInfo.inc"
+
#endif
diff --git a/lib/Target/UniCore/Makefile b/lib/Target/UniCore/Makefile
index bcac019..7fc8895 100644
--- a/lib/Target/UniCore/Makefile
+++ b/lib/Target/UniCore/Makefile
@@ -11,7 +11,9 @@ LIBRARYNAME = LLVMUniCoreCodeGen
TARGET = UniCore
# Make sure that tblgen is run, first thing.
-BUILT_SOURCES =
+BUILT_SOURCES = UniCoreGenRegisterInfo.inc \
+# UniCoreGenInstrInfo.inc \
+# UniCOreGenSubtargetInfo.inc
DIRS = TargetInfo MCTargetDesc
diff --git a/lib/Target/UniCore/UniCore.h b/lib/Target/UniCore/UniCore.h
index 833b861..bf82f6a 100644
--- a/lib/Target/UniCore/UniCore.h
+++ b/lib/Target/UniCore/UniCore.h
@@ -20,6 +20,11 @@
namespace llvm {
class UniCoreTargetMachine;
+ class FunctionPass;
+ class formatted_raw_ostream;
+
+ FunctionPass *createUniCoreISelDag(UniCoreTargetMachine &TM,
+ CodeGenOpt::Level OptLevel);
} // end namespace llvm;
#endif
diff --git a/lib/Target/UniCore/UniCore.td b/lib/Target/UniCore/UniCore.td
new file mode 100644
index 0000000..eb10e4f
--- /dev/null
+++ b/lib/Target/UniCore/UniCore.td
@@ -0,0 +1,57 @@
+//===-- UniCore.td - Describe the UniCore Target Machine ---*- tablegen
-*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+// This is the top level entry point for the UniCore target.
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Target-independent interfaces
+//===----------------------------------------------------------------------===//
+
+include "llvm/Target/Target.td"
+
+//===----------------------------------------------------------------------===//
+// Register File, Calling Conv, Instruction Descriptions
+//===----------------------------------------------------------------------===//
+
+include "UniCoreRegisterInfo.td"
+//include "UniCoreSchedule.td"
+//include "UniCoreCallingConv.td"
+//include "UniCoreInstrInfo.td"
+
+//===----------------------------------------------------------------------===//
+// UniCore Subtarget features //
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// UniCore processors supported.
+//===----------------------------------------------------------------------===//
+class Proc<string Name, list<SubtargetFeature> Features>
+ : Processor<Name, NoItineraries, Features>;
+
+def : Proc<"unicore32", []>;
+
+//===----------------------------------------------------------------------===//
+// Instruction Descriptions
+//===----------------------------------------------------------------------===//
+
+//def UniCoreInstrInfo : InstrInfo;
+
+//def UniCoreAsmWriter : AsmWriter {
+// string AsmWriterClassName = "InstPrinter";
+// bit isMCAsmWriter = 1;
+//}
+
+//===----------------------------------------------------------------------===//
+// Target Declaration
+//===----------------------------------------------------------------------===//
+
+def UniCore : Target {
+// let InstructionSet = UniCoreInstrInfo;
+// let AssemblyWriters = [UniCoreAsmWriter];
+}
diff --git a/lib/Target/UniCore/UniCoreRegisterInfo.cpp
b/lib/Target/UniCore/UniCoreRegisterInfo.cpp
new file mode 100644
index 0000000..7843ad1
--- /dev/null
+++ b/lib/Target/UniCore/UniCoreRegisterInfo.cpp
@@ -0,0 +1,37 @@
+//===-- UniCoreRegisterInfo.cpp - UniCore Register Information ----------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains the UniCore implementation of the TargetRegisterInfo
+// class.
+//
+//===----------------------------------------------------------------------===//
+
+#define DEBUG_TYPE "unicore-reg-info"
+
+#include "UniCoreRegisterInfo.h"
+#include "UniCore.h"
+#include "UniCoreTargetMachine.h"
+#include "llvm/Function.h"
+#include "llvm/CodeGen/MachineFrameInfo.h"
+#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/Target/TargetMachine.h"
+#include "llvm/Target/TargetOptions.h"
+#include "llvm/ADT/BitVector.h"
+#include "llvm/Support/ErrorHandling.h"
+
+#define GET_REGINFO_TARGET_DESC
+#include "UniCoreGenRegisterInfo.inc"
+
+using namespace llvm;
+
+UniCoreRegisterInfo::UniCoreRegisterInfo(UniCoreTargetMachine &tm,
+ const TargetInstrInfo &tii)
+ : UniCoreGenRegisterInfo(UniCore::PC), TM(tm), TII(tii) {
+}
diff --git a/lib/Target/UniCore/UniCoreRegisterInfo.h
b/lib/Target/UniCore/UniCoreRegisterInfo.h
new file mode 100644
index 0000000..912e1f8
--- /dev/null
+++ b/lib/Target/UniCore/UniCoreRegisterInfo.h
@@ -0,0 +1,37 @@
+//=- UniCoreRegisterInfo.h - UniCore Register Information Impl -*- C++ -*-==//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains the UniCore implementation of the MRegisterInfo class.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_TARGET_UNICOREREGISTERINFO_H
+#define LLVM_TARGET_UNICOREREGISTERINFO_H
+
+#include "llvm/Target/TargetRegisterInfo.h"
+
+#define GET_REGINFO_HEADER
+#include "UniCoreGenRegisterInfo.inc"
+
+namespace llvm {
+
+class TargetInstrInfo;
+class UniCoreTargetMachine;
+
+struct UniCoreRegisterInfo : public UniCoreGenRegisterInfo {
+private:
+ UniCoreTargetMachine &TM;
+ const TargetInstrInfo &TII;
+public:
+ UniCoreRegisterInfo(UniCoreTargetMachine &tm, const TargetInstrInfo &tii);
+};
+
+} // end namespace llvm
+
+#endif // LLVM_TARGET_UNICOREREGISTERINFO_H
diff --git a/lib/Target/UniCore/UniCoreRegisterInfo.td
b/lib/Target/UniCore/UniCoreRegisterInfo.td
new file mode 100644
index 0000000..c46067d
--- /dev/null
+++ b/lib/Target/UniCore/UniCoreRegisterInfo.td
@@ -0,0 +1,72 @@
+//===-- UniCoreRegisterInfo.td - UniCore Register defs -----------*- tablegen
-*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Declarations that describe the CPU0 register file
+//===----------------------------------------------------------------------===//
+
+
+class UniCoreGPRReg<bits<5> num, string n> : Register<n> {
+ field bits<5> Num = num;
+ let Namespace = "UniCore";
+}
+
+//===----------------------------------------------------------------------===//
+// Registers
+//===----------------------------------------------------------------------===//
+
+def A1 : UniCoreGPRReg< 0, "r0">, DwarfRegNum<[0]>;
+def A2 : UniCoreGPRReg< 1, "r1">, DwarfRegNum<[1]>;
+def A3 : UniCoreGPRReg< 2, "r2">, DwarfRegNum<[2]>;
+def A4 : UniCoreGPRReg< 3, "r3">, DwarfRegNum<[3]>;
+def R4 : UniCoreGPRReg< 4, "r4">, DwarfRegNum<[6]>;
+def R5 : UniCoreGPRReg< 5, "r5">, DwarfRegNum<[7]>;
+def R6 : UniCoreGPRReg< 6, "r6">, DwarfRegNum<[6]>;
+def R7 : UniCoreGPRReg< 7, "r7">, DwarfRegNum<[7]>;
+def R8 : UniCoreGPRReg< 8, "r8">, DwarfRegNum<[8]>;
+def R9 : UniCoreGPRReg< 9, "r9">, DwarfRegNum<[9]>;
+def R10 : UniCoreGPRReg< 10, "r10">, DwarfRegNum<[10]>;
+def R11 : UniCoreGPRReg< 11, "r11">, DwarfRegNum<[11]>;
+def R12 : UniCoreGPRReg< 12, "r12">, DwarfRegNum<[12]>;
+def R13 : UniCoreGPRReg< 13, "r13">, DwarfRegNum<[13]>;
+def R14 : UniCoreGPRReg< 14, "r14">, DwarfRegNum<[14]>;
+def R15 : UniCoreGPRReg< 15, "r15">, DwarfRegNum<[15]>;
+def R16 : UniCoreGPRReg< 16, "r16">, DwarfRegNum<[16]>;
+def R17 : UniCoreGPRReg< 17, "r17">, DwarfRegNum<[17]>;
+def R18 : UniCoreGPRReg< 18, "r18">, DwarfRegNum<[18]>;
+def R19 : UniCoreGPRReg< 19, "r19">, DwarfRegNum<[19]>;
+def R20 : UniCoreGPRReg< 20, "r20">, DwarfRegNum<[20]>;
+def R21 : UniCoreGPRReg< 21, "r21">, DwarfRegNum<[21]>;
+def R22 : UniCoreGPRReg< 22, "r22">, DwarfRegNum<[22]>;
+def R23 : UniCoreGPRReg< 23, "r23">, DwarfRegNum<[23]>;
+def R24 : UniCoreGPRReg< 24, "r24">, DwarfRegNum<[24]>;
+def SB : UniCoreGPRReg< 25, "r25">, DwarfRegNum<[25]>;
+def SL : UniCoreGPRReg< 26, "r26">, DwarfRegNum<[26]>;
+def FP : UniCoreGPRReg< 27, "r27">, DwarfRegNum<[27]>;
+def IP : UniCoreGPRReg< 28, "r28">, DwarfRegNum<[28]>;
+def SP : UniCoreGPRReg< 29, "r29">, DwarfRegNum<[29]>;
+def LR : UniCoreGPRReg< 30, "r30">, DwarfRegNum<[30]>;
+def PC : UniCoreGPRReg< 31, "pc">, DwarfRegNum<[31]>;
+
+
+//===----------------------------------------------------------------------===//
+// Register Classes
+//===----------------------------------------------------------------------===//
+
+def GPRRegs : RegisterClass<"UniCore", [i32], 32, (add
+ // Reserved
+ R16,
+ // Return Values and Arguments
+ A1, A2, A3, A4,
+ // Not preserved across procedure calls
+ R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15,
+ // Callee save
+ R17, R18, R19, R20, R21, R22, R23, R24, SB, SL, FP, IP, SP, LR,
+ // Reserved
+ PC)>;
diff --git a/lib/Target/UniCore/UniCoreTargetMachine.cpp
b/lib/Target/UniCore/UniCoreTargetMachine.cpp
index beaf5d9..26ce684 100644
--- a/lib/Target/UniCore/UniCoreTargetMachine.cpp
+++ b/lib/Target/UniCore/UniCoreTargetMachine.cpp
@@ -13,6 +13,9 @@
#include "UniCoreTargetMachine.h"
#include "UniCore.h"
+#include "llvm/PassManager.h"
+#include "llvm/CodeGen/Passes.h"
+#include "llvm/MC/MCAsmInfo.h"
#include "llvm/Support/TargetRegistry.h"
using namespace llvm;
@@ -23,9 +26,9 @@ extern "C" void LLVMInitializeUniCoreTarget() {
UniCoreTargetMachine::
UniCoreTargetMachine(const Target &T, StringRef TT,
- StringRef CPU, StringRef FS, const TargetOptions &Options,
- Reloc::Model RM, CodeModel::Model CM,
- CodeGenOpt::Level OL)
+ StringRef CPU, StringRef FS, const TargetOptions &Options,
+ Reloc::Model RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL)
: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL)
{
}
diff --git a/lib/Target/UniCore/UniCoreTargetMachine.h
b/lib/Target/UniCore/UniCoreTargetMachine.h
index ad2aa9c..d760593 100644
--- a/lib/Target/UniCore/UniCoreTargetMachine.h
+++ b/lib/Target/UniCore/UniCoreTargetMachine.h
@@ -14,19 +14,25 @@
#ifndef UNICORE_TARGETMACHINE_H
#define UNICORE_TARGETMACHINE_H
+#include "UniCoreRegisterInfo.h"
+#include "llvm/DataLayout.h"
+#include "llvm/Target/TargetFrameLowering.h"
#include "llvm/Target/TargetMachine.h"
namespace llvm {
class formatted_raw_ostream;
class UniCoreTargetMachine : public LLVMTargetMachine {
+ const DataLayout DL; // Calculates type size & alignment
public:
UniCoreTargetMachine(const Target &T, StringRef TT,
- StringRef CPU, StringRef FS,
- const TargetOptions &Options,
- Reloc::Model RM, CodeModel::Model CM,
- CodeGenOpt::Level OL);
+ StringRef CPU, StringRef FS,
+ const TargetOptions &Options,
+ Reloc::Model RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL);
+
+ virtual const DataLayout *getDataLayout() const { return &DL;}
};
} // End llvm namespace
--
1.7.10.2 (Apple Git-33)
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