[llvm-uc] [PATCH 3/3] Add UniCoreISelDAGToDAG

  • From: Chen Wei-Ren <chenwj@xxxxxxxxxxxxxxxxx>
  • To: llvm-uc@xxxxxxxxxxxxx
  • Date: Sat, 1 Dec 2012 00:27:41 +0800

  Add UniCoreISelDAGToDAG.cpp, and add pattern for ret instruction
in UniCoreInstrInfo.td.

Signed-off-by: Chen Wei-Ren <chenwj@xxxxxxxxxxxxxxxxx>
---
 lib/Target/UniCore/UniCoreISelDAGToDAG.cpp  |  109 +++++++++++++++++++++++++++
 lib/Target/UniCore/UniCoreInstrInfo.td      |    8 ++-
 lib/Target/UniCore/UniCoreTargetMachine.cpp |   25 ++++++
 lib/Target/UniCore/UniCoreTargetMachine.h   |    2 +
 4 files changed, 143 insertions(+), 1 deletions(-)
 create mode 100644 lib/Target/UniCore/UniCoreISelDAGToDAG.cpp

diff --git a/lib/Target/UniCore/UniCoreISelDAGToDAG.cpp 
b/lib/Target/UniCore/UniCoreISelDAGToDAG.cpp
new file mode 100644
index 0000000..7629ed8
--- /dev/null
+++ b/lib/Target/UniCore/UniCoreISelDAGToDAG.cpp
@@ -0,0 +1,109 @@
+//==-- UniCoreISelDAGToDAG.cpp - A dag to dag inst selector for UniCore --==//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines an instruction selector for the UniCore target.
+//
+//===----------------------------------------------------------------------===//
+
+#include "UniCore.h"
+#include "UniCoreTargetMachine.h"
+#include "UniCoreISelLowering.h"
+#include "llvm/DerivedTypes.h"
+#include "llvm/Function.h"
+#include "llvm/Intrinsics.h"
+#include "llvm/CallingConv.h"
+#include "llvm/Constants.h"
+#include "llvm/CodeGen/MachineFrameInfo.h"
+#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/SelectionDAG.h"
+#include "llvm/CodeGen/SelectionDAGISel.h"
+#include "llvm/Target/TargetLowering.h"
+#include "llvm/Support/Compiler.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/raw_ostream.h"
+
+using namespace llvm;
+
+/// UniCoreDAGToDAGISel - UniCore specific code to select UniCore machine
+/// instructions for SelectionDAG operations.
+///
+namespace {
+  class UniCoreDAGToDAGISel : public SelectionDAGISel {
+    const UniCoreTargetLowering &Lowering;
+    //const UniCoreSubtarget &Subtarget;
+
+  public:
+    UniCoreDAGToDAGISel(UniCoreTargetMachine &TM, CodeGenOpt::Level OptLevel)
+      : SelectionDAGISel(TM, OptLevel),
+        Lowering(*TM.getTargetLowering())
+    {}
+
+    virtual const char *getPassName() const {
+      return "UniCore DAG->DAG Pattern Instruction Selection";
+    }
+
+    /// getI16Imm - Return a target constant with the specified value, of type
+    /// i16.
+    inline SDValue getI16Imm(uint64_t Imm) {
+      return CurDAG->getTargetConstant(Imm, MVT::i16);
+    }
+
+    /// getI32Imm - Return a target constant with the specified value, of type
+    /// i32.
+    inline SDValue getI32Imm(uint64_t Imm) {
+      return CurDAG->getTargetConstant(Imm, MVT::i32);
+    }
+    
+    // Include the pieces autogenerated from the target description.
+    #include "UniCoreGenDAGISel.inc"
+
+  private:
+    SDNode *Select(SDNode *N);
+  };
+}  // end anonymous namespace
+
+/// createUniCoreISelDag - This pass converts a legalized DAG into a
+/// UniCore-specific DAG, ready for instruction scheduling.
+///
+FunctionPass *llvm::createUniCoreISelDag(UniCoreTargetMachine &TM,
+                                          CodeGenOpt::Level OptLevel) {
+  return new UniCoreDAGToDAGISel(TM, OptLevel);
+}
+
+SDNode *UniCoreDAGToDAGISel::Select(SDNode *Node) {
+  DebugLoc dl = Node->getDebugLoc();
+
+  // Dump information about the Node being selected
+  DEBUG(errs() << "Selecting: ");
+  DEBUG(Node->dump(CurDAG));
+  DEBUG(errs() << "\n");
+
+  // If we have a custom node, we already have selected!
+  if (Node->isMachineOpcode()) {
+    DEBUG(errs() << "== ";
+          Node->dump(CurDAG);
+          errs() << "\n");
+    return NULL;
+  }
+
+  // Select the default instruction
+  SDNode *ResNode = SelectCode(Node);
+
+  DEBUG(errs() << "=> ");
+  if (ResNode == NULL || ResNode == Node)
+    DEBUG(Node->dump(CurDAG));
+  else
+    DEBUG(ResNode->dump(CurDAG));
+  DEBUG(errs() << "\n");
+
+  return ResNode;
+}
diff --git a/lib/Target/UniCore/UniCoreInstrInfo.td 
b/lib/Target/UniCore/UniCoreInstrInfo.td
index 4fc936a..9dadfda 100644
--- a/lib/Target/UniCore/UniCoreInstrInfo.td
+++ b/lib/Target/UniCore/UniCoreInstrInfo.td
@@ -28,7 +28,7 @@ def SDT_UniCoreCallSeqEnd   : SDCallSeqEnd<[SDTCisVT<0, i32>, 
SDTCisVT<1, i32>]>
 // UniCore specific nodes
 
//===----------------------------------------------------------------------===//
 
-def retflag       :  SDNode<"UniCoreISD::RET_FLAG", SDTNone,
+def ret           :  SDNode<"UniCoreISD::Ret", SDTNone,
                             [SDNPHasChain, SDNPOptInGlue]>;
 def callseq_start :  SDNode<"ISD::CALLSEQ_START", SDT_UniCoreCallSeqStart,
                             [SDNPHasChain, SDNPOutGlue]>;
@@ -45,3 +45,9 @@ def callseq_end   :  SDNode<"ISD::CALLSEQ_END",   
SDT_UniCoreCallSeqEnd,
 let neverHasSideEffects = 1 in
 // Just a slot to make the build progress success.
 def NOP : UniCoreInst<(outs), (ins), "nop", []>;
+
+let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
+  def Ret : UniCoreInst<(outs), (ins),
+                        "ret",
+                        [(ret)]>;
+}
diff --git a/lib/Target/UniCore/UniCoreTargetMachine.cpp 
b/lib/Target/UniCore/UniCoreTargetMachine.cpp
index 28f1d04..325a726 100644
--- a/lib/Target/UniCore/UniCoreTargetMachine.cpp
+++ b/lib/Target/UniCore/UniCoreTargetMachine.cpp
@@ -37,3 +37,28 @@ UniCoreTargetMachine(const Target &T, StringRef TT,
     TLInfo(*this)
 {
 }
+
+namespace {
+/// UniCore Code Generator Pass Configuration Options.
+class UniCorePassConfig : public TargetPassConfig {
+public:
+  UniCorePassConfig(UniCoreTargetMachine *TM, PassManagerBase &PM)
+    : TargetPassConfig(TM, PM) {}
+
+  UniCoreTargetMachine &getUniCoreTargetMachine() const {
+    return getTM<UniCoreTargetMachine>();
+  }
+
+  virtual bool addInstSelector();
+};
+} // namespace
+
+TargetPassConfig *UniCoreTargetMachine::createPassConfig(PassManagerBase &PM) {
+  return new UniCorePassConfig(this, PM);
+}
+
+bool UniCorePassConfig::addInstSelector() {
+  // Install an instruction selector.
+  addPass(createUniCoreISelDag(getUniCoreTargetMachine(), getOptLevel()));
+  return false;
+}
diff --git a/lib/Target/UniCore/UniCoreTargetMachine.h 
b/lib/Target/UniCore/UniCoreTargetMachine.h
index e78c2f5..8fff21a 100644
--- a/lib/Target/UniCore/UniCoreTargetMachine.h
+++ b/lib/Target/UniCore/UniCoreTargetMachine.h
@@ -51,6 +51,8 @@ namespace llvm {
     virtual const UniCoreTargetLowering *getTargetLowering() const {
       return &TLInfo;
     }
+
+    virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
   };
 } // End llvm namespace
 
-- 
1.7.3.4


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  • » [llvm-uc] [PATCH 3/3] Add UniCoreISelDAGToDAG - Chen Wei-Ren