Hallo in die Runde,
wer mag denn zu unten genanntem Vortrag kommen? Könnt euch ja kurz melden.
Grüße
Sebastian
----- Forwarded message from Michael Roitzsch <mroi@xxxxxxxxxxxxxxxxxxxx> -----
Date: Wed, 25 Nov 2015 13:17:31 +0100
From: Michael Roitzsch <mroi@xxxxxxxxxxxxxxxxxxxx>
To: ezag@xxxxxxxxxxxxxxxxxxxx
Subject: next EZAG on Friday, November 27th
X-Mailer: Apple Mail (2.3096.5)
Dear friends of EZAG,
the next talk will take place this Friday at the usual time and place (1PM, APB
E001). Andreas Wiese will defend his Diploma thesis:
Integration and Management of Automatically Generated Hardware Accelerators
on the Linux OS
Long time the panacea for making computers faster was increasing CPU clock
frequency. As this turned out to be not feasible ad infinitum, the trend
moved to increase the number of CPUs in a system while retaining moderate
speeds. Today it becomes apparent that this way is not infinite either.
Current research expects the next phase of evolution to be hardware
acceleration.
Accelerating things in hardware usually meant to build specialised hardware
that does special tasks faster and hence more efficiently than a general
purpose CPU. However, developing and building hardware is a expensive task.
Additionally, needing to have a specialised circuit for every specialised
task one might encounter is not perfect at all.
The gap between CPUs and concrete ICs is closed by FPGAs, Field Programmable
Gate Arrays. These are microchips that can be programmed, and that not like a
CPU is programmed, but the effective wiring of the chip can be modified. This
allows rather cheap development and prototyping of hardware that will be
actually built as an IC later, but also promises a flexible way to accelerate
even exotic tasks. However, programming FPGAs still requires a decent
understanding of hardware design. Various research projects exist to make
programming FPGAs easier by automating it.
One example for such a research project is the GCC plugin written by Gerald
Hempel at the Embedded Systems chair of TU Dresden. This GCC plugin operates
on unmodified C source code and not only generates a software executable, but
also tries to identify loops that make good candidates for hardware
acceleration on an FPGA and outputs an FPGA programming for those loops.
These automatically generated software and hardware accelerators are
currently intended to run on bare-metal, hence with full control over the
hardware, no memory protection and no virtual memory management.
In this work I will implement a framework to integrate those hardware
accelerators into a generic Linux system. This framework will provide a
mechanism to automatically load the adjacent bitfiles when executing a
program having accelerators and a kernel driver to access these accelerators
from userland.
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