[PCB_FORUM] vias hole and SMT pads
- From: "William Billereau" <william.billereau@xxxxxxx>
- To: <icu-pcb-forum@xxxxxxxxxxxxx>
- Date: Wed, 9 Mar 2005 15:45:02 +0100
Hello all again.
Is there a way in Allegro to check (some kind of DRCs) that via holes are
not inside the SMT pad and maybe if a minimum distance is respected. I had a
look in Constraints but did not find anything.
Thanks.
William.
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