[PCB_FORUM] Re: electrical constraint manager, timing

  • From: "Austin Franklin" <austin@xxxxxxxxxxxx>
  • To: <icu-pcb-forum@xxxxxxxxxxxxx>
  • Date: Mon, 4 Jul 2005 21:17:56 -0400

Hi Sam,

> I set the clock up in in ecset in NETS folder.PCLK is set up to
> be 2300-2500 mils in length. The delta tolerance for the rest of
> the match group is 200mils =/- 10 mils. Yet when i auto route my
> clk is about 3000 mils and the rest fo the match group are about
> 4500 mils. Where do i set up the prop delay of the PCLK?

I'm not clear on exactly what you are doing here, and perhaps on what you
are trying to do.  Do you want a relative delay group (all the signals are
simply relative to each other or to one signal...the target), or do you want
them to all be fixed lengths (between a min and a max absolute length)?

It sounds to me (which is contrary to what I thought you wanted), that you
need specific lengths.  If you do, then you don't use relative prop delay,
but total etch length.  Let me know what you are trying to do, and I can
tell you how to do it.  I believe you only need to use one, total etch
length or relative prop delay.

Regards,

Austin

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