[PCB_FORUM] Re: electrical constraint manager, timing

  • From: <sjcharles@xxxxxxx>
  • To: <icu-pcb-forum@xxxxxxxxxxxxx>
  • Date: Mon, 4 Jul 2005 19:24:50 -0400

I set the clock up in in ecset in NETS folder.PCLK is set up to be 2300-2500 
mils in length. The delta tolerance for the rest of the match group is 200mils 
=/- 10 mils. Yet when i auto route my clk is about 3000 mils and the rest fo 
the match group are about 4500 mils. Where do i set up the prop delay of the 
PCLK?
> 
> From: "Austin Franklin" <austin@xxxxxxxxxxxx>
> Date: 2005/06/30 Thu AM 11:28:44 EDT
> To: <icu-pcb-forum@xxxxxxxxxxxxx>
> Subject: [PCB_FORUM] Re: electrical constraint manager, timing
> 
> Under net/routing/relative prop delay, set up a group that contains your
> clock and other signals you want related to this clock.  Set the group match
> length value in the group name heading under "delta:tolerance", such as
> "0:-300" (note the "=", typically 300 will mean +- 300), and it will then be
> assigned to all the signals in that group.  Then, select the clock and set
> it as "target".
> 
> Regards,
> 
> Austin
> 
> > -----Original Message-----
> > From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
> > [mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx]On Behalf Of
> > sjcharles@xxxxxxx
> > Sent: Thursday, June 30, 2005 11:12 AM
> > To: icu-pcb-forum@xxxxxxxxxxxxx
> > Subject: [PCB_FORUM] electrical constraint manager, timing
> >
> >
> > Group: how do i set up a constraint for my clock signal to arrive
> > at it destination where it is equal to or less the arrival of the
> > data signals.
> > I'm using pcb si 610. any suggestions would be appreciated.
> > Thanks, Sam
> 
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